View SSD1331_7802714.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

solomon systech semiconductor technical data this document contains information on a ne w pro duct. specificatio ns and in formatio n herein are subj ect to change w i thout notice. http://www.solo mon-systech.com SSD1331 rev 1.2 p 1/68 nov 2007 cop y right ? 200 7 solo mo n s y st ech li mite d advance information 96rgb x 64 dot matrix oled/pled segment/common driver with controller SSD1331 http://
solom on s y s t e c h nov 2007 p 2/68 rev 1.2 SSD1331 content s contents ....................................................................................................................... .................................. 2 1 gerenal i n fo rmation ............................................................................................................ ......... 6 2 features ....................................................................................................................... ....................... 6 3 orderi ng in formation ........................................................................................................... ........ 6 4 block di agram .................................................................................................................. ................ 7 5 SSD1331z gold bump di e pad as si gnment ................................................................................ 8 6 pin descri ption ................................................................................................................ ................ 12 7 functional block de scriptions .............................................................................................. 15 7.1 mcu i nterfa ce s electi o n ................................................................................................................. 15 7.1.1 6800-seri es paralle l interface ................................................................................................. ..... 15 7.1.2 8080-seri es paralle l interface ................................................................................................. ..... 16 7.1.3 serial in terfac e ............................................................................................................... .............. 17 7.2 c ommand d eco d er ............................................................................................................................. 18 7.3 o scillator c ircuit and d isplay t ime g enerato r ............................................................................ 18 7.3.1 oscillator ..................................................................................................................... ................. 18 7.3.2 fr s y nc hroniz a tion ............................................................................................................. ......... 19 7.4 r eset c ircuit ............................................................................................................................... ...... 19 7.5 g raphic d ispla y d ata ram (gddram) ............................................................................................ 20 7.5.1 gddram s t ru c ture ............................................................................................................... ....... 20 7.5.2 data bus to ram mapping under different input mode ............................................................... 20 7.5.3 ram mapping and differe nt color depth mode............................................................................ 21 7.6 g ra y s cale d eco d er ......................................................................................................................... 21 7.7 seg / com d riving bl ock .................................................................................................................. 23 7.8 c ommon an d s eg ment d rivers .......................................................................................................... 24 7.9 p ow e r on and off seq uence ........................................................................................................... 27 8 command table .................................................................................................................. ............. 28 8.1 d ata r ead / w rite .............................................................................................................................. 34 9 command desc riptio ns ........................................................................................................... ..... 35 9.1 f undamental c ommand ...................................................................................................................... 35 9.1.1 set column a ddress (15h)....................................................................................................... .... 35 9.1.2 set row addr es s (75h) .......................................................................................................... ...... 35 9.1.3 set contrast for color a, b, c (81h, 82h, 83h) ........................................................................... 36 9.1.4 mas t er current control (87h) ................................................................................................... .... 36 9.1.5 set second p r e-charge speed fo r color a, b, c (8ah) ............................................................... 37 9.1.6 set re-map & data format (a0h) ............................................................................................... 37 9.1.7 set dis p lay st art line (a1h)................................................................................................... ...... 42 9.1.8 set dis p lay o ffs et (a2h) ....................................................................................................... ....... 42 9.1.9 set displ a y m ode (a 4h ~ a7h) ................................................................................................... . 45 9.1.10 set multiplex ratio (a 8h) ...................................................................................................... ....... 45 9.1.11 dim mode s e tting ( abh) ......................................................................................................... ...... 45 9.1.12 set mas t er config uration (adh) ................................................................................................. .. 45 9.1.13 set dis p lay on/off (a ch / aeh / afh) ...................................................................................... 45 9.1.14 power save mode (b 0h) .......................................................................................................... .... 46 9.1.15 phase 1 and 2 period ad j u stment (b1h) ..................................................................................... 46 9.1.16 set dis p lay clock divide ratio/ os c illator frequenc y (b3h) ....................................................... 46 9.1.17 set gray sc ale table (b 8h) ..................................................................................................... .... 46 9.1.18 enable li near gray scale tabl e (b 9h) ........................................................................................ 47 9.1.19 set pre-charge voltage (b bh) ................................................................................................... ... 47 9.1.20 set v co mh vo ltage (beh) .............................................................................................................. 47 9.1.21 nop (b ch, bd h, e3h) ............................................................................................................ ..... 47 9.1.22 set command lock (fdh) ......................................................................................................... .. 47 9.2 graphi c acce lerati on comma nd set description .......................................................... 48 9.2.1 draw li ne (2 1h) ................................................................................................................ ........... 48 9.2.2 draw rec t an gle (2 2h) ........................................................................................................... ....... 48
SSD1331 rev 1.2 p 3/68 nov 2007 s o l o mo n s y st ec h 9.2.3 copy (23h) ..................................................................................................................... .............. 49 9.2.4 dim window (24h) ............................................................................................................... ........ 49 9.2.5 clear windo w (2 5h) ............................................................................................................. ........ 50 9.2.6 fill enable/di sabl e (26h) ...................................................................................................... ........ 50 9.2.7 continuous horiz ontal & vert ical sc rolling setup (27h) .............................................................. 51 9.2.8 deactivate scr olling (2eh) ..................................................................................................... ....... 51 9.2.9 ac tivate s c ro lling (2fh) ....................................................................................................... ......... 51 10 maximum ra tings................................................................................................................ ............. 52 11 dc character istics ............................................................................................................. .......... 53 12 ac character istics ............................................................................................................. .......... 54 13 applicatio n examp le ............................................................................................................ ........ 58 14 package options ................................................................................................................ ............ 59 14.1 ssd133 1z d ie t ra y i nf or mation ................................................................................................... 59 14.2 ssd133 1u1 r 1 cof package dimensions.............................................................................. 60 14.3 ssd133 1u1 r 1 cof package pin assignment ...................................................................... 62 14.4 ssd133 1u3 r 1 cof package dimensions.............................................................................. 64 14.5 ssd133 1u3 r 1 cof package pin assignment ...................................................................... 66
solom on s y s t e c h nov 2007 p 4/68 rev 1.2 SSD1331 tables table 1 - ordering information ................................................................................................. ........................... 6 table 2 - ss d1331z di e pad coor dinates......................................................................................... ................. 9 table 3 - bus inte rfac e s e lec tion .............................................................................................. ......................... 12 table 4 - mcu interfac e as s i gnment un der different bus interfac e mode ......................................................... 15 table 5 - control pins of 6800 interfac e ....................................................................................... ..................... 15 table 6 - control pins of 8080 interfac e (form 1) .............................................................................. ............... 16 table 7 - control pins of 8080 interfac e (form 2) .............................................................................. ............... 16 table 8 - control pins of serial interfac e ..................................................................................... ...................... 17 table 9 - dat a bus usage under differe nt bus wi dth and co lor depth mode...................................................... 20 table 10 - co mmand t able ....................................................................................................... ........................ 28 table 11 - address increm ent table (a ut omatic) ................................................................................. .............. 34 table 12 - illus t ration of di fferent com out put s e ttings ....................................................................... .............. 39 table 13 - example of set display offs et and display start line wit h no remap ............................................ 43 table 14 - example of set display offs et and display start line wit h rem a p ................................................. 44 table 15 - res u lt of change of brightnes s by di m window command ............................................................ 49 table 16 - maxi mum rati ngs ..................................................................................................... ........................ 52 table 17 - dc ch arac teristic s .................................................................................................. ......................... 53 table 18 - ac ch arac teristic s .................................................................................................. .......................... 54 table 19 - 6800-series mp u parallel interfac e timing charac teris tic s ........................................................... . 55 table 20 - 8080-series mp u parallel interfac e timing charac teris tic s ........................................................... . 56 table 21 - serial interfac e timing charac teris tics ............................................................................. ............... 57 table 22 - SSD1331u1 r1 pin as s i gnment .......................................................................................... ............. 63 table 23 - SSD1331u3 r1 pin as s i gnment .......................................................................................... ............. 67
SSD1331 rev 1.2 p 5/68 nov 2007 s o l o mo n s y st ec h figures figure 1 - SSD1331 bloc k diagram ............................................................................................... ..................... 7 figure 2 - SSD1331z die drawing ................................................................................................ ...................... 8 figure 3 - SSD1331z alignm ent mark dimens ions .................................................................................. ......... 11 figure 4 - display data read back proc edure - insertion of dummy read .......................................................... 15 figure 5 ? example of write procedur e in 8080 parall el interfac e m ode .......................................................... 16 figure 6 ? example of read procedur e in 8080 parall el interfac e m ode .......................................................... 16 figure 7 - display data read back proc edure - insertion of dummy read .......................................................... 17 figure 8 - write proc edure in spi mode ......................................................................................... ................... 17 figure 9 - oscilla tor circuit .................................................................................................. .............................. 18 figure 10 - 65k color de pth graphic display da ta ra m struc ture ................................................................. . 20 figure 11 - 256-col o r mode mappi ng ............................................................................................. ................... 21 figure 12 - relation bet we en gdram cont ent and g r ay scal e table entry for thre e colo rs in 65 k color m ode 21 figure 13 - ill u stration of relation between gra phi c display ram value and gray scale cont rol ........................ 22 figure 14 - i ref current setting by res i stor value ............................................................................................ 23 figure 15 - i seg curre nt v s v cc setting at con s tant i ref , contras t = ffh ........................................................... 23 figure 16 - s egment and comm on driv er bloc k di ag ram ............................................................................ .... 24 figure 17 - s egment and comm on driv er signal waveform .......................................................................... .. 25 figure 18 - gray sc ale cont rol by pwm in segment ............................................................................... ......... 26 figure 19 : the powe r on s equenc e .............................................................................................. .................. 27 figure 20 : the powe r off s e quenc e ............................................................................................. ................. 27 figure 21 - e x ample of column an d row address p o inter movement ............................................................. 35 figure 22 - effect of setting the sec ond pre-charge under different speeds ..................................................... 37 figure 23 - a ddress pointer movement of horiz ontal a ddress incr ement mode .............................................. 37 figure 24 - a ddress pointer movement of vertic al addres s inc r ement mode .................................................. 37 figure 25 - e x ample of co l u mn address mapping .................................................................................. .......... 38 figure 26 - com pins hardware c onfiguration (mux ratio: 64) .................................................................... ... 40 figure 27 ? t r ansition be tween differ ent modes ................................................................................. .............. 45 figure 28 - t y pical o scill ator freq uen cy adju s tment b y b3 comman d (v dd = 2 .7v) .......................................... 46 figure 29 - e x ample of gamma c o rrec tion by gray scale table setting ............................................................ . 47 figure 30 ? t y pical pre-charge volt age l e vel setting by command bbh. .......................................................... 47 figure 31 - e x ample of draw line command ....................................................................................... ............ 48 figure 32 - e x ample of dr aw rec tangle command .................................................................................. ........ 48 figure 33 - e x ample of copy command ............................................................................................ ............... 49 figure 34 - e x ample of copy + clear = mo ve command ............................................................................ .... 50 figure 35 - e x amples of conti nuous horizontal an d vertical sc rolli ng c o mmand s e tup .................................. 51 figure 36 - 6800-serie s parallel interface c h arac teris t ic s ..................................................................... ............. 55 figure 37 - 8080-ser ies parallel interface c harac teris t ic s (form 1) ............................................................ ....... 56 figure 38 - 8080-ser ies parallel interface c harac teris t ic s (form 2) ............................................................ ....... 56 figure 39 - s e rial interf ace c h arac teris tic s ................................................................................... ..................... 57 figure 40 - a pplication ex ample for ss d1331u1r1 ................................................................................ ......... 58 figure 41 - die tray information ............................................................................................... ......................... 59 figure 42 - s s d1331u1r 1 outline dr awing ........................................................................................ .............. 60 figure 43 - s s d1331u1r1 pi n ass i gnment drawing ................................................................................. ........ 62 figure 44 - s s d1331u3r 1 outline dr awing ........................................................................................ .............. 64 figure 45 - s s d1331u3r1 pi n ass i gnment drawing ................................................................................. ........ 66
solom on s y s t e c h nov 2007 p 6/68 rev 1.2 SSD1331 1 gerenal information the ssd133 1 is a single chip cmos oled/pled driver with 288 se gment s and 64 co mmon s outp ut, sup p o r ting u p to 96 rgb x 64 dot matrix displa y. this chi p is d e si gne d for comm on cathod e type oled/ple d panel. the ssd13 3 1 had embe d ded graphi c display data ram (gddram). it support s with 8, 9, 16 bits 8080 / 6800 parallel interface a s well a s seri al perip he ral in terf ace. it has 25 6-step contra st and 6 5k colo r cont rol. to facilitate communi cation bet ween lower operating vo ltages m cu, it has separat e power for i/o interface logic. ssd13 31 is suitable for mobile p h one s, mp3, mp 4 and oth e r ind u stri al d e vice s. 2 feat ure s ? re solutio n : 96rgb x 64 d o t matrix pan el ? 65k colo r de p t h supp ort by embe dde d 96 x64x16 bit gddram di spl a y buffer ? powe r su pply : o v dd = 2.4v to 3.5v for ic logi c o v cc = 8.0v to 18.0v for panel d r iving o v ddi o = 1.6v to v dd for mcu interfac e ? segment ma ximum sou r ce cu rre nt: 200ua ? comm on maximum sink current: 60ma ? 256 ste p co ntra st control for the ea ch col or compo nent plus 16 step maste r cu rre n t control ? pin sele ctabl e mcu interf ace o 8/9/16 bits 68 00-se rie s pa rallel interfa c e o 8/9/16 bits 80 80-se rie s parallel interfa c e o serial peri ph eral interfa c e ? color swapping function (rgb <-> bgr) ? gra phi c acce leratin g com m and (gac) set with conti nuou s hori zo ntal, vertical and di ago nal scrolli ng ? prog ramm abl e fram e rate ? wide ran ge o f operatin g temperature: -4 0 to 85 c 3 ordering information table 1 - ord e ring inform ation orderin g part nu mb er seg com pack ag e f o r m r efer en ce rema rk ssd13 31z 96 x3 64 cog page 8, 59 ? min seg pad p i tch: 40.2 um ? min com pad pitch: 41.8 um SSD1331u1r1 96 x3 64 cof page 60 ? 35mm film, 5 sprocket ho le ? 8 bit or spi interface ? output lead pit ch: 0.06mm for seg, 0.09mm for com ssd13 31u 3r 1 96 x3 64 cof page 64 ? 35mm film, 4 sprocket ho le ? 8 bit or spi interface ? output lead pit ch: 0.06mm for seg, 0.09mm for com
SSD1331 rev 1.2 p 7/68 nov 2007 s o l o mo n s y st ec h 4 block di agram f i g u re 1 - ssd133 1 blo ck diag ram mcu interface gddram gray scale decoder common drivers segment drivers common drivers seg/com driving block oscillator display timing generator command decoder (even) (odd) res# cs# d/c# e(rd#) r/w #(wr#) bs[3:0] d[15:0] v cc v dd v ddio v ss v lss cl cls fr i ref v comh com0 com2 com4 . . . com58 com60 com62 com6 3 com6 1 com5 9 . . . com5 com3 com1 sc 9 5 sb 9 5 sa 9 5 sc 9 4 sb 9 4 sa 9 4 sc 9 3 sb 9 3 sa 9 3 . . . sc 2 sb 2 sa 2 sc 1 sb 1 sa 1 sc 0 sb 0 sa 0 gpio0 gpio1 av dd
solom on s y s t e c h nov 2007 p 8/68 rev 1.2 SSD1331 5 SSD1331z gold bump die pad assignment f i g u re 2 - ssd133 1z die dr a w in g pad 1 die size 13.1mm x 1.58mm die height 457um min i/o pad pitch 76.2 um min seg pad pitch 40.2 um min com pad pitch 41.8 um bump height nominal 15um b u mp si ze pad 1-163 50um x 72um pad164-195, 486-517 72um x 28um pad 196-485 28um x 72um alignment ma rk + shape (5446.0, -402.0) 75um x 75um + shape (-5446.0, -402.0) 75um x 75um SSD1331z pad 1,2,3,?->16 3 gold bumps fac e up x y
SSD1331 rev 1.2 p 9/68 nov 2007 s o l o mo n s y st ec h t a b l e 2 - ssd133 1z die pad co o r d i n a tes p a d n o . p a d na m e x - ax i s y - ax i s p a d n o . p a d na m e x - ax i s y - ax i s p a d n o . p a d na m e x - ax i s y - ax i s 1 n c - 6 31 9. 4 -71 2. 5 81 b s 2 - 76. 2 - 7 1 2 . 5 1 61 n c 61 67. 0 - 71 2. 5 2 n c - 62 43. 2 - 71 2. 5 82 v ss 0. 0 - 7 1 2 . 5 1 62 n c 6243 . 2 -71 2. 5 3 n c - 6 1 6 7. 0 -71 2. 5 83 b s 3 7 6. 2 - 7 1 2 . 5 1 63 n c 631 9. 4 - 71 2. 5 4 n c - 60 90. 8 - 71 2. 5 84 v d d i o 1 52. 4 - 7 1 2 . 5 1 64 c o m 31 642 0. 1 - 6 47. 9 5 n c - 6 01 4. 6 -71 2. 5 85 v d d i o 228 . 6 - 7 1 2 . 5 1 65 c o m 30 642 0. 1 - 606 . 1 6 n c - 5 791 . 2 -71 2. 5 86 i r e f 304 . 8 - 7 1 2 . 5 1 66 c o m 29 642 0. 1 - 5 64. 3 7 v c c - 5 71 5. 0 - 71 2. 5 87 v c c 38 1 . 0 - 7 1 2 . 5 1 67 c o m 28 642 0. 1 - 5 22. 5 8 v c c -56 38. 8 - 71 2. 5 88 v c c 457 . 2 - 7 1 2 . 5 1 68 c o m 27 642 0. 1 - 4 80. 7 9 v c c -55 62. 6 - 71 2. 5 89 v c c 533 . 4 - 7 1 2 . 5 1 69 c o m 26 642 0. 1 - 4 38. 9 1 0 v ls s -54 86. 4 - 71 2. 5 90 f r 609 . 6 - 7 1 2 . 5 1 70 c o m 25 642 0. 1 - 397 . 1 1 1 v ls s - 5 41 0. 2 - 71 2. 5 91 c l 685 . 8 - 7 1 2 . 5 1 71 c o m 24 642 0. 1 - 3 55. 3 1 2 v ls s -53 34. 0 - 71 2. 5 92 v ss 762 . 0 - 7 1 2 . 5 1 72 c o m 23 642 0. 1 - 31 3. 5 1 3 v ls s -52 57. 8 - 71 2. 5 93 c ls 838 . 2 - 7 1 2 . 5 1 73 c o m 22 642 0. 1 - 271 . 7 1 4 v ls s -51 81 . 6 - 71 2. 5 94 v d d i o 91 4. 4 - 7 1 2 . 5 1 74 c o m 21 642 0. 1 - 2 29. 9 1 5 v ls s - 5 1 0 5. 4 - 71 2. 5 95 v d d i o 990 . 6 - 7 1 2 . 5 1 75 c o m 20 642 0. 1 - 1 88. 1 1 6 v l s s -50 29. 2 - 71 2. 5 9 6 v d d i o 1 0 6 6 . 8 - 7 1 2 . 5 1 7 6 c om 1 9 642 0. 1 - 1 46. 3 1 7 v l s s -49 53. 0 - 71 2. 5 9 7 v d d i o 1 1 4 3 . 0 - 7 1 2 . 5 1 7 7 c om 1 8 642 0. 1 - 1 04. 5 1 8 v ls s -48 76. 8 - 71 2. 5 98 c sb 1 2 1 9. 2 - 7 1 2 . 5 1 78 c om 1 7 642 0. 1 - 62 . 7 1 9 v ls s -48 00. 6 - 71 2. 5 99 v ss 1 29 5. 4 - 7 1 2 . 5 1 79 c om 1 6 642 0. 1 - 20 . 9 2 0 v ls s -47 24. 4 - 71 2. 5 1 0 0 r e sb 1 3 71 . 6 - 7 1 2 . 5 1 80 c om 1 5 642 0. 1 20. 9 21 v ls s -46 48. 2 - 71 2. 5 1 01 v d d i o 1 44 7. 8 - 7 1 2 . 5 1 81 c o m 1 4 642 0. 1 62. 7 2 2 v s s - 45 72. 0 - 71 2. 5 1 0 2 v d d i o 1 52 4. 0 - 7 1 2 . 5 1 82 c o m 1 3 642 0. 1 1 04 . 5 2 3 v s s - 44 95. 8 - 71 2. 5 1 0 3 d c 1 60 0. 2 - 7 1 2 . 5 1 83 c om 1 2 642 0. 1 1 46 . 3 2 4 v s s - 4 4 19 . 6 - 7 12 . 5 1 0 4 v s s 16 7 6 . 4 - 7 1 2 . 5 18 4 c o m 11 6 4 2 0 . 1 18 8 . 1 2 5 b g g n d - 43 43. 4 - 71 2. 5 1 0 5 r w 1 75 2. 6 - 7 1 2 . 5 1 85 c om 1 0 642 0. 1 22 9. 9 2 6 vd d - 42 67. 2 - 71 2. 5 1 0 6 e 1 82 8. 8 - 7 1 2 . 5 1 86 c o m 9 642 0. 1 2 71 . 7 2 7 vd d - 41 91 . 0 -71 2. 5 1 0 7 v d d i o 1 90 5. 0 - 7 1 2 . 5 1 87 c om 8 642 0. 1 3 1 3 . 5 2 8 vd d - 41 1 4 . 8 -71 2. 5 1 0 8 v d d 1 9 81 . 2 - 7 1 2 . 5 1 88 c om 7 642 0. 1 35 5. 3 2 9 vd d i o - 40 38. 6 - 71 2. 5 1 0 9 v d d 20 57. 4 - 7 1 2 . 5 1 89 c o m 6 642 0. 1 3 97. 1 3 0 vd d i o - 39 62. 4 - 71 2. 5 1 1 0 v d d 2 1 3 3. 6 - 7 1 2 . 5 1 90 c o m 5 642 0. 1 43 8. 9 31 vd d i o - 38 86. 2 - 71 2. 5 1 1 1 d 0 22 09. 8 - 7 1 2 . 5 1 91 c o m 4 642 0. 1 48 0. 7 32 v c c - 38 1 0 . 0 - 7 1 2 . 5 1 1 2 d 1 2 28 6 . 0 - 71 2. 5 1 9 2 c o m 3 6 4 20 . 1 5 22 . 5 3 3 vc c - 37 33. 8 - 71 2. 5 1 1 3 d 2 23 62. 2 - 7 1 2 . 5 1 93 c o m 2 642 0. 1 56 4. 3 3 4 vc c - 36 57. 6 - 71 2. 5 1 1 4 d 3 24 38. 4 - 7 1 2 . 5 1 94 c o m 1 642 0. 1 6 06. 1 3 5 v s s b - 3 581 . 4 -71 2. 5 1 1 5 d 4 2 51 4. 6 - 7 1 2 . 5 1 95 c o m 0 642 0. 1 64 7. 9 3 6 v s s b -35 05. 2 - 71 2. 5 1 1 6 d 5 25 90. 8 - 7 1 2 . 5 1 96 v ls s 5908 . 5 64 3. 6 3 7 v s s b -34 29. 0 - 71 2. 5 1 1 7 d 6 26 67. 0 - 7 1 2 . 5 1 97 sa 0 582 8. 1 64 3. 6 3 8 gd r - 33 52. 8 - 71 2. 5 1 1 8 d 7 27 43. 2 - 7 1 2 . 5 1 98 sb 0 5787 . 9 64 3. 6 3 9 gd r - 32 76. 6 - 71 2. 5 1 1 9 d 8 2 81 9. 4 - 7 1 2 . 5 1 99 s c 0 5747 . 7 64 3. 6 4 0 gd r - 32 00. 4 - 71 2. 5 1 2 0 d 9 28 95. 6 - 7 1 2 . 5 200 s a 1 5707 . 5 64 3. 6 41 gd r - 3 1 2 4 . 2 -71 2 . 5 1 2 1 d 1 0 2 971 . 8 - 7 1 2 . 5 20 1 s b 1 5667 . 3 64 3. 6 4 2 gd r - 30 48. 0 - 71 2. 5 1 2 2 d 1 1 30 48. 0 - 7 1 2 . 5 202 s c 1 562 7. 1 64 3. 6 4 3 gd r - 2 971 . 8 -71 2. 5 1 2 3 d 1 2 3 1 2 4. 2 - 7 1 2 . 5 203 sa 2 5586 . 9 64 3. 6 4 4 gd r - 28 95. 6 - 71 2. 5 1 2 4 d 1 3 32 00. 4 - 7 1 2 . 5 204 sb 2 5546 . 7 64 3. 6 4 5 vd d b - 2 81 9. 4 - 71 2. 5 1 2 5 d 1 4 32 76. 6 - 7 1 2 . 5 205 sc 2 5506 . 5 64 3. 6 4 6 vd d b -27 43. 2 - 71 2. 5 1 2 6 d 1 5 33 52. 8 - 7 1 2 . 5 206 sa 3 5466. 3 64 3. 6 4 7 vd d b -26 67. 0 - 71 2. 5 1 2 7 v s s 34 29. 0 - 7 1 2 . 5 207 sb 3 542 6. 1 64 3. 6 4 8 vd d b -25 90. 8 - 71 2. 5 1 2 8 t r 1 1 35 05. 2 - 7 1 2 . 5 208 sc 3 5385. 9 64 3. 6 4 9 vd d b - 2 51 4. 6 - 71 2. 5 1 2 9 t r 1 0 3 581 . 4 - 7 1 2 . 5 209 sa 4 5345 . 7 64 3. 6 5 0 vd d - 24 38. 4 - 71 2. 5 1 3 0 t r 9 3 6 57. 6 - 7 1 2 . 5 2 1 0 sb 4 5305 . 5 64 3. 6 51 vd d i o - 23 62. 2 - 71 2. 5 1 31 t r 8 37 33. 8 - 7 1 2 . 5 21 1 sc 4 5265 . 3 64 3. 6 5 2 vd d - 22 86. 0 - 71 2. 5 1 3 2 t r 7 3 81 0. 0 - 7 1 2 . 5 2 1 2 sa 5 522 5. 1 6 4 3 . 6 5 3 vd d - 22 09. 8 - 71 2. 5 1 3 3 t r 6 3 8 86. 2 - 7 1 2 . 5 2 1 3 sb 5 5 1 84. 9 6 4 3 . 6 5 4 f b - 2 1 3 3. 6 - 71 2. 5 1 3 4 v s s 39 62. 4 - 7 1 2 . 5 21 4 sc 5 51 44. 7 64 3. 6 5 5 v b r e f - 20 57. 4 - 71 2. 5 1 3 5 t r 5 40 38. 6 - 7 1 2 . 5 21 5 sa 6 51 04. 5 64 3. 6 5 6 v s s - 1 9 81 . 2 -71 2. 5 1 3 6 t r 4 41 1 4. 8 - 7 1 2 . 5 21 6 s b 6 5064 . 3 64 3. 6 5 7 g p i o 0 - 1 90 5. 0 -71 2. 5 1 3 7 t r 3 41 91 . 0 - 7 1 2 . 5 21 7 s c 6 502 4. 1 64 3. 6 5 8 gp i o 1 - 1 82 8. 8 -71 2. 5 1 3 8 t r 2 42 67. 2 - 7 1 2 . 5 21 8 sa 7 4983 . 9 64 3. 6 5 9 vd d i o - 1 75 2. 6 -71 2. 5 1 3 9 t r 1 43 43. 4 - 7 1 2 . 5 21 9 sb 7 4943. 7 64 3. 6 6 0 v c i r - 1 67 6. 4 - 71 2. 5 1 4 0 t r 0 4 41 9. 6 - 7 1 2 . 5 220 sc 7 4903. 5 64 3. 6 61 v c i r - 1 60 0. 2 - 71 2. 5 1 41 v s s 44 95. 8 - 7 1 2 . 5 22 1 sa 8 4863. 3 64 3. 6 6 2 v c i r - 1 52 4. 0 - 71 2. 5 1 4 2 v c om h 45 72. 0 - 7 1 2 . 5 222 sb 8 482 3. 1 64 3. 6 6 3 v c i r - 1 44 7. 8 - 71 2. 5 1 4 3 v c om h 46 48. 2 - 7 1 2 . 5 223 sc 8 4782 . 9 64 3. 6 6 4 v c i r -1 3 71 . 6 - 71 2. 5 1 4 4 v c om h 47 24. 4 - 7 1 2 . 5 224 sa 9 4742 . 7 64 3. 6 6 5 vd d - 1 29 5. 4 -71 2. 5 1 4 5 v d d 48 00. 6 - 7 1 2 . 5 225 sb 9 4702 . 5 64 3. 6 6 6 vd d - 1 2 1 9 . 2 -71 2. 5 1 4 6 v d d 48 76. 8 - 7 1 2 . 5 226 sc 9 4662 . 3 64 3. 6 6 7 vd d - 1 1 43 . 0 -71 2. 5 1 4 7 v d d i o 49 53. 0 - 7 1 2 . 5 227 s a 1 0 462 2. 1 64 3. 6 6 8 vd d - 1 06 6. 8 -71 2. 5 1 4 8 v d d i o 50 29. 2 - 7 1 2 . 5 228 s b 1 0 458 1 . 9 64 3. 6 6 9 a v d d -990 . 6 -71 2 . 5 1 4 9 v c c 5 1 0 5 . 4 - 7 1 2 . 5 229 s c 1 0 454 1 . 7 6 4 3 . 6 7 0 a v d d -91 4 . 4 -71 2. 5 1 5 0 v c c 51 81 . 6 - 7 1 2 . 5 230 sa 1 1 450 1 . 5 64 3. 6 71 vd d i o - 838 . 2 -71 2. 5 1 51 v c c 52 57. 8 - 7 1 2 . 5 23 1 sb 1 1 446 1 . 3 64 3. 6 7 2 vd d i o - 762 . 0 -71 2. 5 1 5 2 v c c 53 34. 0 - 7 1 2 . 5 232 sc 1 1 44 21 . 1 64 3. 6 7 3 vd d i o - 685 . 8 -71 2. 5 1 5 3 v c c 5 41 0. 2 - 7 1 2 . 5 233 s a 1 2 4380 . 9 64 3. 6 7 4 vd d i o - 609 . 6 -71 2. 5 1 5 4 v c c 54 86. 4 - 7 1 2 . 5 234 s b 1 2 4340 . 7 64 3. 6 7 5 vd d i o - 533 . 4 -71 2. 5 1 5 5 n c 55 62. 6 - 7 1 2 . 5 235 s c 1 2 4300 . 5 64 3. 6 7 6 vd d i o - 457 . 2 -71 2. 5 1 5 6 v l s s 56 38. 8 - 7 1 2 . 5 236 s a 1 3 4260 . 3 64 3. 6 7 7 b s 0 - 38 1 . 0 - 71 2. 5 1 5 7 vl ss 5 7 1 5 . 0 - 7 1 2 . 5 237 s b 1 3 422 0. 1 6 4 3 . 6 7 8 v s s - 304 . 8 -71 2. 5 1 5 8 n c 5 791 . 2 - 7 1 2 . 5 238 s c 1 3 41 79. 9 64 3. 6 7 9 b s 1 - 228 . 6 -71 2. 5 1 5 9 n c 6 01 4. 6 - 7 1 2 . 5 239 s a 1 4 41 39. 7 64 3. 6 8 0 vd d i o - 1 52 . 4 - 71 2. 5 1 6 0 n c 60 90. 8 - 7 1 2 . 5 240 s b 1 4 4099 . 5 64 3. 6
solom on s y s t e c h nov 2007 p 10/68 rev 1.2 SSD1331 p a d n o . p a d n a m e x - a x i s y - a x is p a d no . p a d n a m e x - a x is y - a x is p a d no . p a d n a m e x - a x is y - a x is 241 sc 1 4 4 059. 3 643. 6 321 sb 41 84 3. 3 64 3. 6 40 1 s a 6 8 -2493. 3 643 . 6 242 sa 1 5 401 9. 1 643. 6 3 22 sc 41 80 3. 1 64 3. 6 40 2 s b 6 8 -2533. 5 643 . 6 243 sb 1 5 3 978. 9 643. 6 3 23 sa 42 76 2. 9 64 3. 6 40 3 s c 6 8 -2573. 7 643 . 6 244 sc 1 5 3 938. 7 643. 6 3 24 sb 42 72 2. 7 64 3. 6 40 4 s a 6 9 -261 3 . 9 643 . 6 245 sa 1 6 3 898. 5 643. 6 3 25 sc 42 68 2. 5 64 3. 6 40 5 s b 6 9 -2654. 1 643 . 6 246 sb 1 6 3 858. 3 643. 6 3 26 sa 43 64 2. 3 64 3. 6 40 6 s c 6 9 -2694. 3 643 . 6 247 sc 1 6 381 8. 1 643. 6 3 27 sb 43 60 2. 1 64 3. 6 40 7 s a 7 0 -2734. 5 643 . 6 248 sa 1 7 3 777. 9 643. 6 3 28 sc 43 56 1 . 9 64 3. 6 40 8 s b 7 0 -2774. 7 643 . 6 249 sb 1 7 3 737. 7 643. 6 3 29 sa 44 52 1 . 7 64 3. 6 40 9 s c 7 0 -281 4 . 9 643 . 6 250 sc 1 7 3 697. 5 643. 6 3 30 sb 44 48 1 . 5 64 3. 6 41 0 s a 7 1 -2855. 1 643 . 6 251 sa 1 8 3 657. 3 643. 6 331 sc 44 44 1 . 3 64 3. 6 41 1 s b 7 1 -2895. 3 643 . 6 252 sb 1 8 361 7. 1 643. 6 3 32 sa 45 40 1 . 1 64 3. 6 41 2 s c 7 1 -2935. 5 643 . 6 253 sc 1 8 3 576. 9 643. 6 3 33 sb 45 36 0. 9 64 3. 6 41 3 s a 7 2 -2975. 7 643 . 6 254 sa 1 9 3 536. 7 643. 6 3 34 sc 45 32 0. 7 64 3. 6 41 4 s b 7 2 -301 5 . 9 643 . 6 255 sb 1 9 3 496. 5 643. 6 3 35 sa 46 28 0. 5 64 3. 6 41 5 s c 7 2 -3056. 1 643 . 6 256 sc 1 9 3 456. 3 643. 6 3 36 sb 46 24 0. 3 64 3. 6 41 6 s a 7 3 -3096. 3 643 . 6 257 sa 20 341 6. 1 643. 6 3 37 sc 46 20 0. 1 64 3. 6 41 7 s b 7 3 -31 36 . 5 643 . 6 258 sb 20 3 375. 9 643. 6 3 38 sa 47 1 5 9. 9 64 3. 6 41 8 s c 7 3 -31 76 . 7 643 . 6 259 sc 20 3 335. 7 643. 6 3 39 sb 47 1 1 9. 7 64 3. 6 41 9 s a 7 4 -321 6 . 9 643 . 6 260 sa 21 3 295. 5 643. 6 3 40 sc 47 7 9. 5 64 3. 6 42 0 sb 7 4 -3257. 1 643 . 6 261 sb 21 3 255. 3 643. 6 341 sa 48 -8 1 . 3 64 3. 6 42 1 s c 7 4 -3297. 3 643 . 6 262 sc 21 321 5. 1 643. 6 3 42 sb 48 -1 21 . 5 64 3. 6 42 2 sa 7 5 -3337. 5 643 . 6 263 sa 22 31 74. 9 643. 6 3 43 sc 48 -1 61 . 7 64 3. 6 42 3 sb 7 5 -3377. 7 643 . 6 264 sb 22 31 34. 7 643. 6 3 44 sa 49 -2 01 . 9 64 3. 6 42 4 sc 7 5 -341 7 . 9 643 . 6 265 sc 22 3 094. 5 643. 6 3 45 sb 49 -2 42. 1 64 3. 6 42 5 s a 7 6 -3458. 1 643 . 6 266 sa 23 3 054. 3 643. 6 3 46 sc 49 -28 2. 3 64 3. 6 42 6 s b 7 6 -3498. 3 643 . 6 267 sb 23 301 4. 1 643. 6 3 47 sa 50 -32 2. 5 64 3. 6 42 7 s c 7 6 -3538. 5 643 . 6 268 sc 23 2 973. 9 643. 6 3 48 sb 50 -36 2. 7 64 3. 6 42 8 s a 7 7 -3578. 7 643 . 6 269 sa 24 2 933. 7 643. 6 3 49 sc 50 -40 2. 9 64 3. 6 42 9 s b 7 7 -361 8 . 9 643 . 6 270 sb 24 2 893. 5 643. 6 3 50 sa 51 -4 43. 1 64 3. 6 43 0 s c 7 7 -3659. 1 643 . 6 271 sc 24 2 853. 3 643. 6 351 sb 51 -48 3. 3 64 3. 6 43 1 s a 7 8 -3699. 3 643 . 6 272 sa 25 281 3. 1 643. 6 3 52 sc 51 -52 3. 5 64 3. 6 43 2 s b 7 8 -3739. 5 643 . 6 273 sb 25 2 772. 9 643. 6 3 53 sa 52 -56 3. 7 64 3. 6 43 3 s c 7 8 -3779. 7 643 . 6 274 sc 25 2 732. 7 643. 6 3 54 sb 52 -60 3. 9 64 3. 6 43 4 s a 7 9 -381 9 . 9 643 . 6 275 sa 26 2 692. 5 643. 6 3 55 sc 52 -6 44. 1 64 3. 6 43 5 s b 7 9 -3860. 1 643 . 6 276 sb 26 2 652. 3 643. 6 3 56 sa 53 -68 4. 3 64 3. 6 43 6 s c 7 9 -3900. 3 643 . 6 277 sc 26 261 2. 1 643. 6 3 57 sb 53 -72 4. 5 64 3. 6 43 7 s a 8 0 -3940. 5 643 . 6 278 sa 27 2571 . 9 643. 6 3 58 sc 53 -76 4. 7 64 3. 6 43 8 s b 8 0 -3980. 7 643 . 6 279 sb 27 2531 . 7 643. 6 3 59 sa 54 -80 4. 9 64 3. 6 43 9 s c 8 0 -4020. 9 643 . 6 280 sc 27 2491 . 5 643. 6 3 60 sb 54 -8 45. 1 64 3. 6 44 0 s a 8 1 -4061 . 1 643 . 6 281 sa 28 2451 . 3 643. 6 361 sc 54 -88 5. 3 64 3. 6 44 1 s b 8 1 -41 01 . 3 643 . 6 282 sb 28 241 1 . 1 643. 6 3 62 sa 55 -92 5. 5 64 3. 6 44 2 s c 8 1 -41 41 . 5 643 . 6 283 sc 28 2 370. 9 643. 6 3 63 sb 55 -96 5. 7 64 3. 6 44 3 s a 8 2 -41 81 . 7 643 . 6 284 sa 29 2 330. 7 643. 6 3 64 sc 55 -1 0 05. 9 64 3. 6 44 4 s b 8 2 -4221 . 9 643 . 6 285 sb 29 2 290. 5 643. 6 3 65 sa 56 -1 0 46. 1 64 3. 6 44 5 s c 8 2 -4262. 1 643 . 6 286 sc 29 2 250. 3 643. 6 3 66 sb 56 -1 0 86. 3 64 3. 6 44 6 s a 8 3 -4302. 3 643 . 6 287 sa 30 221 0. 1 643. 6 3 67 sc 56 -1 1 2 6. 5 64 3. 6 44 7 s b 8 3 -4342. 5 643 . 6 288 sb 30 21 69. 9 643. 6 3 68 sa 57 -1 1 6 6. 7 64 3. 6 44 8 s c 8 3 -4382. 7 643 . 6 289 sc 30 21 29. 7 643. 6 3 69 sb 57 -1 2 06. 9 64 3. 6 44 9 s a 8 4 -4422. 9 643 . 6 290 sa 31 2 089. 5 643. 6 3 70 sc 57 -1 2 47. 1 64 3. 6 45 0 s b 8 4 -4463. 1 643 . 6 291 sb 31 2 049. 3 643. 6 371 sa 58 -1 2 87. 3 64 3. 6 45 1 s c 8 4 -4503. 3 643 . 6 292 sc 31 2009 . 1 643. 6 3 72 sb 58 -1 3 27. 5 64 3. 6 45 2 s a 8 5 -4543. 5 643 . 6 293 sa 32 1 968. 9 643. 6 3 73 sc 58 -1 3 67. 7 64 3. 6 45 3 s b 8 5 -4583. 7 643 . 6 294 sb 32 1 928. 7 643. 6 3 74 sa 59 -1 4 07. 9 64 3. 6 45 4 s c 8 5 -4623. 9 643 . 6 295 sc 32 1 888. 5 643. 6 3 75 sb 59 -1 4 48. 1 64 3. 6 45 5 s a 8 6 -4664. 1 643 . 6 296 sa 33 1 848. 3 643. 6 3 76 sc 59 -1 4 88. 3 64 3. 6 45 6 s b 8 6 -4704. 3 643 . 6 297 sb 33 1 808. 1 643. 6 3 77 sa 60 -1 5 28. 5 64 3. 6 45 7 s c 8 6 -4744. 5 643 . 6 298 sc 33 1 767. 9 643. 6 3 78 sb 60 -1 5 68. 7 64 3. 6 45 8 s a 8 7 -4784. 7 643 . 6 299 sa 34 1 727. 7 643. 6 3 79 sc 60 -1 6 08. 9 64 3. 6 45 9 s b 8 7 -4824. 9 643 . 6 300 sb 34 1 687. 5 643. 6 3 80 sa 61 -1 6 49. 1 64 3. 6 46 0 s c 8 7 -4865. 1 643 . 6 301 sc 34 1 647. 3 643. 6 381 sb 61 -1 6 89. 3 64 3. 6 46 1 s a 8 8 -4905. 3 643 . 6 302 sa 35 1 607. 1 643. 6 3 82 sc 61 -1 7 29. 5 64 3. 6 46 2 s b 8 8 -4945. 5 643 . 6 303 sb 35 1 566. 9 643. 6 3 83 sa 62 -1 7 69. 7 64 3. 6 46 3 s c 8 8 -4985. 7 643 . 6 304 sc 35 1 526. 7 643. 6 3 84 sb 62 -1 8 09. 9 64 3. 6 46 4 s a 8 9 -5025. 9 643 . 6 305 sa 36 1 486. 5 643. 6 3 85 sc 62 -1 8 50. 1 64 3. 6 46 5 s b 8 9 -5066. 1 643 . 6 306 sb 36 1 446. 3 643. 6 3 86 sa 63 -1 8 90. 3 64 3. 6 46 6 s c 8 9 -51 06 . 3 643 . 6 307 sc 36 1 406. 1 643. 6 3 87 sb 63 -1 9 30. 5 64 3. 6 46 7 s a 9 0 -51 46 . 5 643 . 6 308 sa 37 1 365. 9 643. 6 3 88 sc 63 -1 9 70. 7 64 3. 6 46 8 s b 9 0 -51 86 . 7 643 . 6 309 sb 37 1 325. 7 643. 6 3 89 sa 64 -20 1 0. 9 64 3. 6 46 9 sc 9 0 -5226. 9 643 . 6 31 0 s c 37 1 285. 5 643. 6 3 90 sb 64 -20 51 . 1 64 3. 6 47 0 sa 9 1 -5267. 1 643 . 6 31 1 s a 38 1 245. 3 643. 6 391 sc 64 -20 91 . 3 64 3. 6 47 1 sb 9 1 -5307. 3 643 . 6 31 2 s b 38 1 205. 1 643. 6 3 92 sa 65 -21 31 . 5 64 3. 6 47 2 sc 9 1 -5347. 5 643 . 6 31 3 s c 38 1 1 64. 9 643. 6 3 93 sb 65 -21 71 . 7 64 3. 6 47 3 sa 9 2 -5387. 7 643 . 6 31 4 s a 39 1 1 24. 7 643. 6 3 94 sc 65 -22 1 1 . 9 64 3. 6 47 4 s b 9 2 -5427. 9 643 . 6 31 5 s b 39 1 084. 5 643. 6 3 95 sa 66 -22 52. 1 64 3. 6 47 5 s c 9 2 -5468. 1 643 . 6 31 6 s c 39 1 044. 3 643. 6 3 96 sb 66 -22 92. 3 64 3. 6 47 6 s a 9 3 -5508. 3 643 . 6 31 7 s a 40 1 004. 1 643. 6 3 97 sc 66 -23 32. 5 64 3. 6 47 7 s b 9 3 -5548. 5 643 . 6 31 8 s b 40 963. 9 643. 6 3 98 sa 67 -23 72. 7 64 3. 6 47 8 s c 9 3 -5588. 7 643 . 6 31 9 s c 40 923. 7 643. 6 3 99 sb 67 -24 1 2. 9 64 3. 6 47 9 sa 9 4 -5628. 9 643 . 6 320 sa 41 883. 5 643. 6 4 00 sc 67 -24 53. 1 64 3. 6 48 0 s b 9 4 -5669. 1 643 . 6
SSD1331 rev 1.2 p 11/68 nov 2007 s o l o mo n s y st ec h figure 3 - ss d1 3 3 1 z a lignme n t ma rk dime ns ions p a d no . p a d n a m e x - a x i s y - a x is 48 1 s c 94 - 57 09. 3 64 3. 6 48 2 s a 95 - 57 49. 5 64 3. 6 48 3 s b 95 - 57 89. 7 64 3. 6 48 4 s c 95 - 58 29. 9 64 3. 6 48 5 v lss - 591 0. 3 64 3. 6 48 6 c om 32 - 642 0. 1 64 7. 9 48 7 c om 33 - 642 0. 1 60 6. 1 48 8 c om 34 - 642 0. 1 56 4. 3 48 9 c om 35 - 642 0. 1 52 2. 5 49 0 c om 36 - 642 0. 1 48 0. 7 49 1 c om 37 - 642 0. 1 43 8. 9 49 2 c om 38 - 642 0. 1 39 7. 1 49 3 c om 39 - 642 0. 1 35 5. 3 49 4 c om 40 - 642 0. 1 31 3. 5 49 5 c om 41 - 642 0. 1 27 1 . 7 49 6 c om 42 - 642 0. 1 22 9. 9 49 7 c om 43 - 642 0. 1 1 8 8. 1 49 8 c om 44 - 642 0. 1 1 46. 3 49 9 c om 45 - 642 0. 1 1 04. 5 50 0 c om 46 - 642 0. 1 62. 7 50 1 c om 47 - 642 0. 1 20. 9 50 2 c om 48 - 642 0. 1 - 20. 9 50 3 c om 49 - 642 0. 1 - 62. 7 50 4 c om 50 - 642 0. 1 - 1 0 4. 5 50 5 c om 51 - 642 0. 1 - 1 4 6. 3 50 6 c om 52 - 642 0. 1 - 1 88 . 1 50 7 c om 53 - 642 0. 1 - 229 . 9 50 8 c om 54 - 642 0. 1 - 271 . 7 50 9 c om 55 - 642 0. 1 - 31 3. 5 51 0 c om 56 - 642 0. 1 - 355 . 3 51 1 c om 57 - 642 0. 1 - 397 . 1 51 2 c om 58 - 642 0. 1 - 438 . 9 51 3 c om 59 - 642 0. 1 - 480 . 7 51 4 c om 60 - 642 0. 1 - 522 . 5 51 5 c om 61 - 642 0. 1 - 564 . 3 51 6 c om 62 - 642 0. 1 - 606 . 1 51 7 c om 63 - 642 0. 1 -647.9 + sh ape unit in um
solom on s y s t e c h nov 2007 p 12/68 rev 1.2 SSD1331 6 pin des c ription pin name pin t y pe des c ription v dd powe r powe r su pply pin for co re v dd av dd power analog power supply. it must be connected to v dd during operation. v ddio powe r powe r su pply for interface logic level. it s h ould be matc h with the mcu interface voltage level. v ddio must always b e equ al or lo wer th an v dd . v cc powe r powe r su pply for panel d r iving voltage. this i s also the most po sitive power voltage su ppl y pin. v ss powe r gro und pi n v lss powe r analog syste m grou nd pin. v co m h o com sign al d e sel e cte d voltage level. a capa citor should b e co n necte d betwe en this pin a n d v ss . bggn d powe r con ne c t to grou nd v ddb powe r re se rved pin . it should be conn ect to v dd externally. v ssb powe r re se rved pin . it should be conn ecte d to v ss externall y . gdr o re se rved pin . keep nc (i. e. no con ne c tion). fb i re se rved pin . keep nc (i. e. no con ne c tion). v bref o re se rved pin . keep nc (i. e. no con ne c tion). gpio0 i/o re se rved pin . keep nc (i. e. no con ne c tion). gpio1 i/o re se rved pin . keep nc (i. e. no con ne c tion). v cir o re se rved pin . keep nc (i. e. no con ne c tion). bs[3:0] i mcu bu s inte rface sel e ctio n pins. table 3 - bu s interface s election bs[3:0] bus interface selection 0000 spi 0100 8-bit 6800 parallel 0101 16-bit 6800 parallel 0110 8-bit 8080 parallel 0111 16-bit 8080 parallel 1100 9-bit 6800 parallel 1110 9-bit 8080 parallel i ref i this pi n is th e seg ment ou tput current refere nce pin. a resi stor sh ould be con n ected b etwe e n this pin an d v ss to mai n tain the i ref cu rre nt at 10ua. please refer to figure 14 for the details form ul a of resisto r value.
SSD1331 rev 1.2 p 13/68 nov 2007 s o l o mo n s y st ec h pin name pin t y pe des c ription fr o this pi n outp u ts ram writ e synchroni zation sig nal. prope r timing betwee n mcu data writing a nd frame di sp lay timing can be achi eve to preve n t tearing effe ct. keep nc if not used. refer to section 7.3.2 for details usage. cl i this i s extern al clo ck in put pin. whe n interna l clock is e n a b led (i.e. hig h in cls pi n), this pin is no t used an d sho uld be co nne cted to v ss . when internal clo c k is di sabl ed (i.e. l o w in cls pin), this pi n is the extern al clock sou r ce input pin. cls i internal clo c k sele ction pin. whe n this pin is pulled hi gh (i.e. conn ect to v ddio ), inte rnal o s cillator is enabl e (no r mal o peration). whe n this pin is pulled lo w, an external clock sig nal sh ould be con n e cted to cl. cs# i this pi n is th e chip sele ct input co nne cti ng to the mcu. res# i this pin is res e t s i gnal input. when the pin is low, initiali za tion of the chip i s executed. keep this pi n high (i.e. con nect to v ddio ) durin g norm al ope ration. d/c# i this pi n is da ta/comma nd cont rol pin co nne cting to the mcu. whe n the pin is pulled high (i.e. conn ect to v dd io ), the data at d[15:0]will be interp reted a s data. when the pin is pulled low, the data at d[15:0] will be inte rpreted as command. r/w# (wr# ) i this pi n is re ad / write con t rol input pin con n e c ting to the mcu inte rface. whe n interfa c ing to a 68 00-se rie s micr oprocesso r, this pin will be used a s rea d/write (r/w# ) sele ction inp ut. rea d mode will b e ca rri ed out whe n this pi n is pulled high (i.e. c o nnec t to v ddio ) and write mo de when lo w. whe n 8080 interfa c e mod e is selecte d, this pin will be the write (wr# ) input. data write operation is initiated wh e n this pin is pulled low and the chi p is sele ct ed. whe n se rial i nterfa c e is se lected, this pi n r/w# (wr# ) must be con necte d to v ss . e (rd#) i this pi n is m cu inte rfa c e i nput. when interfacing to a 6800-seri e s mi cropr ocessor, this pin w ill be used as the enable (e ) si gnal. re ad/write ope ration is initiated when this pi n is pulle d high (i.e. c o nnec t to v ddio ) and the chi p is sel ected. whe n co nne cting to an 8 080 -micro pro c e s sor, this p i n receives th e rea d (rd# ) sign al. re ad ope ration i s initiated wh en this pin i s pulled l o w a nd the chip i s sele ct ed. whe n se rial i nterfa c e is se lected, this pi n e(rd# ) mu st be co nne ct ed to v ss . d[15:0] i/o the s e pin s are bi-di r e c tion al data bu s conne cting to the mcu data bus. unu s e d pin s are recomme nded to tie lo w. (except for d2 pi n in se rial mod e ) refer to sec t ion 7.1 for differe nt bus inte rface co nne ct ion. sa[95:0] sb[95:0] sc[95:0] o the s e pi ns p r ovide th e o led segm en t driving sign als. th ese pi ns a r e i n hig h imped an ce st ate whe n display is off b y comman d set displ a y of f. the s e 288 segme n t pins are divided in to 3 groups, sa, sb and sc. each gro u p can h a ve differe nt colo r se ttings for colo r a, b and c.
solom on s y s t e c h nov 2007 p 14/68 rev 1.2 SSD1331 pin name pin t y pe des c ription com[6 3 :0] i/o the s e pin s p r ovide the co mmon switch signal s to the oled pa n e l. these pi n s are in hi gh im peda nce stat e whe n displa y is off by comman d set display off. tr[11:0] i testin g re se rved pins. th ese pi ns sho u ld be kept float. nc nc dummy pi ns. these pin s sho uld b e ke pt float and should not be con n e c ted to any other signal pins nor any electrical signal. do not connect nc pins together.
SSD1331 rev 1.2 p 15/68 nov 2007 s o l o mo n s y st ec h 7 functional blo ck de scriptions 7.1 mcu inte rface selection ssd133 1 mcu interfa c e consi s t of 16 d a ta pin and 5 cont ro l pin s . the pin a s sig n ment at different interfa c e mode i s sum m ari z ed in ta ble 4. differe nt mcu mo d e can b e set by hard w a r e sele ction o n bs[3:0] pins (refer to table 3 for bs pins setting) t a b l e 4 - mcu in terface as sig n m en t u n d e r d i fferen t b u s in terface mo d e d1 5 d 1 4 d1 3 d 12 d11 d 1 0 d9 d8 d 7 d6 d5 d4 d3 d2 d 1 d0 e r / w # c s# d / c # res# 8 b / 80 80 rd# w r# c s # d / c # r es# 8 b / 68 00 e r/ w # c s# d/ c # res# 9 b / 80 80 rd# w r# c s # d / c # r es# 9 b / 68 00 e r/ w # c s# d/ c # res# 16 b / 8 0 8 0 rd# w r# c s # d / c # r es# 16 b / 6 8 0 0 e r/ w # c s# d/ c # res# spi nc sdi n sc l k cs # d / c# r e s # ti e l o w tie low ti e l o w ti e l o w d1 5-d0 d8 - d0 d1 5-d0 d a t a / c o m m a n d i n t erf ace co n t r o l s i g n al p in na m e bus inte rf ac e d8-d0 ti e l ow ti e l ow d7-d0 d7-d0 7.1.1 6800- series parallel inte rface a low in r/w# indicates write ope rati on and hi gh i n r/w# in dicates rea d o peration. a low in d/c# indicate s co mmand rea d / write an d high in d/c# indic a tes data read/write. the e input serve s as d a ta latch sig nal while cs# is l o w. data is l a tche d at the falling edg e o f e signal. t a b l e 5 - co n t ro l p i n s o f 6800 in terface func ti on e r / w # c s # d/ c# w r ite c o m m and ll l read s tatus hl l w r ite data ll h read data hl h note (1 ) stands for falli ng e dge of s i gna l (2 ) h stands for high i n sig nal (3 ) l stands for l o w in sig n a l in orde r to match the op erating freq uen cy of display ram with tha t of the micro p ro ce ssor, so me pipeli ne pro c e s sing i s intern ally performe d whi c h req u ire s the i n se rtion of a dummy re ad befor e the first actual displa y data re ad. th is is sho w n in figure 4 figure 4 - di spla y data read back pr o cedur e - ins ertion of du mmy read n n n+1 n+2 r/w# e datab u s wri t e co lu m n address read 1 s t data dumm y read read 2nd data read 3rd data
solom on s y s t e c h nov 2007 p 16/68 rev 1.2 SSD1331 7.1.2 8080- series parallel inte rface a low in d/c# indicate s command re ad/write and high in d/ c# indicates da ta read/ write . a rising e dge of rd# in put se rves a s a d ata read lat c h si gnal whil e cs# is kept low. a rising e dge of wr# in put se rves a s a d ata/comm and write latch signal while cs# is kept l o w. f i g u r e 5 ? examp l e o f w r ite p r o ced u r e in 808 0 p a rallel in terface mo d e cs# wr# d[7:0] d/ c# rd # hi gh low f i g u r e 6 ? examp l e o f read p r o ced u r e in 808 0 p a rallel in terface mo d e cs # wr # d[7:0 ] d/c # rd# high low t a b l e 6 - co n t ro l p i n s o f 8080 in terface (f o rm 1) func ti on rd# w r # c s # d/ c# w r ite c o m m and h ll read status hl l write data h lh read data hlh note (1 ) stands for rising e d g e of signa l (2 ) h stands for high i n sig nal (3 ) l stands for l o w in sig n a l (4 ) refer to f i gu re 37 for form 1 8080 -seri e s mpu parall el inte rface timing charact e ri stics alternatively, e(rd# ) and r/w #(wr# ) can b e ke ep stable while cs# is serve as the data/ comman d latch sign al. t a b l e 7 - co n t ro l p i n s o f 8080 in terface (f o rm 2) func ti on rd# w r # c s # d/ c# w r ite c o m m and h l l read status l h l write data h l h read data l h h note (1) stands for rising e d g e of signa l (2) h stan ds for high i n sign al (3) l stan ds for lo w in si gn al (4 ) refer to figure 38 for form 2 8080 -seri e s mpu parall el inte rface timing charact e ri stics
SSD1331 rev 1.2 p 17/68 nov 2007 s o l o mo n s y st ec h in order to match the op eratin g frequ ency of displ a y ram with that of the micr op ro ce ssor, some pip eline pro c e s sing is internally performed which requires the inse rtion of a dummy rea d befor e the first actual displ ay data re ad. th is is sho w n in figure 7. f i g u r e 7 - dis p lay d a ta r ead b ack p r o ced u r e - in sertio n o f d u mmy rea d n n n+1 n+2 wr# rd# d a tabus wr i t e c o l u m n add res s re ad 1s t da ta du m m y re ad read 2nd data read 3rd data 7.1.3 serial interface the se rial int erfa c e co nsi s ts of serial clo ck sclk (d0 ) , serial data sdin (d1), d/ c# and cs#. sclk is shifted into an 8-bit shift regi ster on every risi ng edge of sclk in the orde r of d7, d6? d0. d/c# is sampl ed on every eighth clo ck a nd th e data byte in the shift re gi ste r is written to the display data ram or comm and regi st er in t h e same clo ck. und er seri al mode, only write ope ration s are allo wed . t a b l e 8 - co n t ro l p i n s o f serial in terface func ti on e r / w # c s # d/ c# w r i t e c om m and t ie lo w t ie lo w l l w r i t e data t ie lo w t ie lo w l h figure 8 - writ e proc e dure in spi mo de d7 d6 d5 d4 d3 d2 d1 d0 sclk(d0) sdin(d1) db1 db2 dbn cs# d/c# sdin/ sclk
solom on s y s t e c h nov 2007 p 18/68 rev 1.2 SSD1331 7.2 command decoder this m odul e determi ne s whethe r the inp ut sho uld be i n terp reted as data or com m and b ased upon th e inpu t of the d/c# pin. if d/c# pin is high, data is written to gra phic di spl ay data ram (g dd ram ) . if it is low, the in puts at d0-d15 are inte rp rete d as a comm and an d it will be decode d and be writte n to the corre s po ndin g co mmand regi st er. 7.3 oscillator circuit and displa y ti me generator 7.3.1 oscillator di vi der internal o s c illator fo sc m u x cl clk dclk display clock cls figure 9 - oscillator circuit this module i s an on-chip low po wer rc oscillator ci rcuitry ( figure 9). the op e r ation clo ck (clk) can b e gene rate d either fro m internal oscillato r or extern al so urce cl pin b y cls pin. if cls pin i s hi gh, intern al oscillator is selected. if cls pin is low, external cl ock from cl pin will be used f o r clk. the frequency of intern al oscill ator f osc can be pro gra m m ed by com m and b3h (set oscill ator freque ncy ) . the di splay cl ock (dclk) for the di spl ay timing gen e r ator i s de rive d from clk. the divisi on facto r ?d? can be programm ed from 1 to 16 by comm a nd b3h. dc lk = f osc / d the fram e fre quen cy of display is dete r mined by the followin g formula. mux of no. k d f f osc frm = whe r e ? d s t ands for c l oc k divide ratio. it is s e t by comma nd b3h a[3:0]. t he divide ratio has the ran ge from 1 to 16. ? k is the numb e r of display clo c ks pe r ro w. the value is derive d by k = phase 1 peri od + pha s e 2 pe rio d + pw63 (l ong e s t cu rre nt driv e pulse width ) = 4 + 7 + 125 = 13 6 at reset ? num ber of m u ltiplex ratio i s set by co m m and a8h. t he re set valu e is 64 ? f osc is the oscillator frequency. it c an be adjusted by command b 3h a[7:4]
SSD1331 rev 1.2 p 19/68 nov 2007 s o l o mo n s y st ec h 7.3.2 fr s y n c hro nization fr syn c h r oni zation sign al can b e used to preve n t tearing effe ct. the sta r ting time to write a new im age to oled driv e r is dep end ed on the mcu writin g sp eed . if mcu ca n finish writing a frame ima g e within on e frame p e ri od, it is classified as fast write mcu. for mcu n eed s lon ger writing time to c o mplete ( m ore than one frame but within two frames) , it is a slo w write o ne. for fas t w r ite mcu: m c u shoul d sta r t to write n e w frame of ram d a ta just after rising e dge of fr pul se a n d sho u ld be fini she d well b e fore the ri sin g edge of the n e xt fr pulse. for slo w w r i t e mcu : mcu sh ould start to write new frame ra m d a ta after the falling ed ge of the 1 st fr pu lse and mu st be finish ed befo r e the risi ng e dge of the 3 rd fr pulse . 7.4 reset circu it whe n res# i nput is pull e d low, the chip is initialized with the followi ng statu s : 1. d i splay is off 2. 64 mux di spl a y mode 3. display sta r t line is set at display ram a ddress 0 4. display offs et s e t to 0 5. no rmal segm ent and di spl ay data colu mn add re ss a nd ro w ad dre ss m appi ng (seg0 mapp e d to add re ss 0 0h and com0 m appe d to add re ss 0 0h) 6. colu mn ad dress co unte r is set at 0 7. maste r co ntra st cont rol re gi ster i s set at 0fh 8. individual con t rast control registe r s of co lor a, b, and c are set at 8 0 h 9. shift registe r data cle a r in se rial interfa c e 10. no rmal di spla y mode (equi valent to a4 comman d ) fast w r ite mc u slo w w r ite mc u ssd13 31 d i spl a yin g memor y upd ates to oled screen one frame fr 100 % 0% memory access process time
solom on s y s t e c h nov 2007 p 20/68 rev 1.2 SSD1331 7.5 graphic di spla y data ram (gddram) 7.5.1 gddr am structure the g d dra m is a bit ma pped static ram holdin g the pattern to be displayed . the ram si ze is 96 x 64 x 16bits. for me ch ani cal flexibility, r e -ma ppin g on both s egme nt and co mm on output s ca n be sel ecte d by software. for verti c al scrolling of th e displ a y, an internal regi st er st orin g d i splay sta r t line ca n be set to control the portio n of the ram data to be map ped to the display. each pixel h as 16 -bit dat a. three sub - pixels for col o r a, b and c have 6 bits, 5 bits and 6 bits re spe c ti vely. the arra nge ment of data pixel in gra p h i c display dat a ram is sho w n bel ow. f i g u r e 10 - 65k co lo r dep t h grap h i c disp la y dat a r a m stru ctu r e 7.5.2 data bus to ram mapping under dif f erent input mode ta ble 9 - da ta bus us a g e un de r diffe re nt b u s w i dt h a n d c o lor de pth mode d a t a b u s bus width color depth input order d15 d14 d13 d 12 d11 d 10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 8 bits 256 x x xxxxxx c 4 c 3 c 2 b 5 b 4 b 3 a 4 a 3 8 bits 65k f o rm at 1 1st x x xxxxxx c 4 c 3 c 2 c 1 c 0 b 5 b 4 b 3 2nd x x xxxxxx b 2 b 1 b 0 a 4 a 3 a 2 a 1 a 0 8 bits 65k f o rm at 2 1st x x xxxxxxxx c 4 c 3 c 2 c 1 c 0 x 2nd x x xxxxxxxx b 5 b 4 b 3 b 2 b 1 b 0 3rd x x xxxxxxxx a 4 a 3 a 2 a 1 a 0 x 16 bits 65k c 4 c 3 c 2 c 1 c 0 b 5 b 4 b 3 b 2 b 1 b 0 a 4 a 3 a 2 a 1 a 0 9 bits 65k 1st x x xxxxx c 4 c 3 c 2 c 1 c 0 x b 5 b 4 b 3 2nd x x xxxxx b 2 b 1 b 0 a 4 a 3 a 2 a 1 a 0 x no r m a l : re m a p : a 4 b5 c4 a 4 b5 c4 a 4 b5 c4 a 4 b5 c4 a 4 b5 c4 a 4 b5 c4 a 3 b4 c3 a 3 b4 c3 a 3 b4 c3 a 3 b4 c3 a 3 b4 c3 a 3 b4 c3 a 2 b3 c2 a 2 b3 c2 a 2 b3 c2 a 2 b3 c2 a 2 b3 c2 a 2 b3 c2 a 1 b2 c1 a 1 b2 c1 a 1 b2 c1 a 1 b2 c1 a 1 b2 c1 a 1 b2 c1 a 0 b1 c0 a 0 b1 c0 a 0 b1 c0 a 0 b1 c0 a 0 b1 c0 a 0 b1 c0 b0 b0 b0 b0 b0 b0 co m normal remap outpu t 0 63 5 6 5 5 6 5 5 6 5 5 6 5 5 6 5 5 6 5 com 0 1 62 com 1 2 61 com 2 : : : 61 2 com 6 1 62 1 com 6 2 63 0 com 6 3 sa0 sb0 sc0 sa1 sb1 sc1 sa2 sb2 sc2 : sa93 sb93 sc93 sa94 sb94 sc94 sa95 sb95 sc95 : : da ta form at ro w a ddress 2 93 93 2 0 95 : co lu m n a ddress seg output 1 95 0 94 1 94 no. of bits of data in this cell
SSD1331 rev 1.2 p 21/68 nov 2007 s o l o mo n s y st ec h 7.5.3 ram mapping and different color depth mode at 65k col o r d epth mod e , color a, b, c are directly ma pped to the ram content. at 256-colo r mode, the ra m content will be filled up to 65k format. f i g u r e 11 - 256-co lo r mo d e map p i n g 65k color c 4 c 3 c 2 c 1 c 0 b 5 b 4 b 3 b 2 b 1 b 0 a 4 a 3 a 2 a 1 a 0 256 color c 4 c 3 c 2 *c 4 *c 4 b 5 b 4 b 3 b 5 *b 5 *b 5 a 4 a 3 *a 4 *a 4 *a 4 sbn sa n sc n note: (1) n = 0 ~ 95 (2) bits with * are copied from correspond ing bits in order to fill up 65k format. 7.6 gra y scale decoder the gray sca le effect is gene rated by cont rollin g the pul se width of segment driver s in cu rrent drive ph ase . the gray sca l e table store s the corre s p ondin g pulse widths of the 63 gray scale levels (g s0~gs6 3). th e wider the pul s e width, the br ighter the pixel will be. a singl e gray scal e table supports all t he three colors a, b and c. th e p u lse width s can be set by softwa r e com m and s. as s h own in figure 12, col o r b sub-pixe l ram data has 6 bits, r eprese n t the 64 gray scale le vels from gs0 to gs63. colo r a and colo r c su b-pixel ram data ha s only 5 bits, represent 32 gray scale levels from gs0, gs2, ?, gs62. f i g u r e 12 - relatio n b e t w ee n gdr a m co n t en t an d g r ay scale tab l e en tr y fo r th ree c o lo rs in 65k c o lo r mo d e colo r a, c ram data (5 bits) colo r b ram data (6 bits) gray scal e default pul se width of gs[0 :63] in terms of dclk 0000 0 0000 00 gs0 0 - 0000 01 gs1 1 0000 1 0000 10 gs2 3 - 0000 11 gs3 5 0001 0 0001 00 gs4 7 : : : : : : : : : : : : 1111 0 1111 00 gs60 119 - 1111 01 gs61 121 1111 1 1111 10 gs62 123 - 1111 11 gs63 125 the du ration of different g s are progra mmable.
solom on s y s t e c h nov 2007 p 22/68 rev 1.2 SSD1331 figure 1 3 - il lu s t ra tion of re l a tion be t w e e n gra phic d i s p l a y r a m v a lue a nd gra y sc a l e c ontrol gray scal e table gray scal e value/dclk s gs0 0 gs1 1 gs2 3 : : gs62 123 gs63 125 segment voltage time v p v lss color a ram data = 00001 gs2 pulse width = 3 dclks color a ram data = 11111 gs62 pulse width = 123 dclks segment voltage time v p v lss color b ram data = 000001 gs1 pulse width = 1 dclks color b ram data = 111111 gs63 pulse width = 125 dclks
SSD1331 rev 1.2 p 23/68 nov 2007 s o l o mo n s y st ec h 7.7 seg / com driving block this blo c k is use d to deriv e the incomi n g power sou r ce s into the different level s of internal use voltag e a n d cu rre nt. ? v cc is the most positive vol t age su pply. ? v co m h is the comm on de selecte d level. it is internally regul ated. ? v lss is the ground p ath of the anal og an d panel cu rre nt. ? i ref is a ref e re nce curre n t sou r ce fo r segme n t current d r ivers i seg . the relatio n ship betwe en referen c e current an d se g m ent cu rrent of a colo r is: i seg = contra st / 256 x i re f x scale f a ct o r in whi c h the cont ra st (0~2 55 ) is set by set contra st comm and; and the scale fact or (1 ~ 16 ) is set by maste r current cont rol comma nd. for exam ple, in ord er to a c hieve i seg = 160ua at ma ximum co ntra st 255, i ref is set to aro un d 10ua. this cu rrent value is obtai ned by con n e c ting an app ropri ate resi st or from i ref pi n t o v ss as shown in figure 14. re comm end ed ra nge for i ref = 10ua +/ - 2ua figure 1 4 - i ref curre nt se tting by re s i s t or va lue since the volt age at i ref pin is v cc ? 3v, the value of resi stor r1 ca n be found a s below. r1 = (voltage at i ref ? v ss ) / i re f = (v cc ? 3) / 10ua 1.3m for v cc = 16v. figure 1 5 - i seg current v s v cc s e tting a t c onsta nt i re f , contra s t = ff h ssd133 1 i ref (voltage at this pin = v cc ? 3) r1 v ss i ref 10ua ty pic a l i se g curre nt vs v cc (i re f = 10 u a , co nt ra s t = f f h ) 140 150 160 170 180 190 200 210 7 9 11 13 15 17 19 v cc (v ) i se g (ua )
solom on s y s t e c h nov 2007 p 24/68 rev 1.2 SSD1331 7.8 common and segment drivers segment driv ers con s ist of 288 (9 6 x 3 colo rs) cu rre n t so urce s to drive oled panel . t he driving current can be adju s ted from 0 to 160 ua with 256 step s by co n t rast setting comm and (8 1h,82h,8 3 h ) . comm on driv ers gene rate sca nning voltage pulse. the block diagram s and wavefo rms of the se gment and co mmon drive r are s h own as follow. figure 1 6 - se gme n t and co mmon dri v er bloc k dia g ram the com m on s are sca nne d sequ entiall y, row by row. if a row is not sele cted, all the pixels on the row are in reverse bi as by driving tho s e commo ns to voltage v co m h a s s h ow n in figure 1 7 in the sca nne d ro w, the pixels on the ro w will be tu rn ed on o r of f by sendi ng the co rre sp on ding data sig nal to the segm e n t pins. if the pixel is turne d off, the se gment curren t is kept at 0. on the othe r hand, the seg m ent driv es to i seg when the pixel is turned o n . v com h non-select row selected row v cc current drive reset v lss v lss common driver segment driver oled pixel i seg
SSD1331 rev 1.2 p 25/68 nov 2007 s o l o mo n s y st ec h fig u re 1 7 - se gme n t a nd common dri v er signa l wav e form com1 v co m h v lss v co m h v lss com0 one frame p erio d non - sele ct r o w selected row com voltage v co m h v lss this row i s selected to turn on time segment voltage v lss waveform for on waveform for off time v p
solom on s y s t e c h nov 2007 p 26/68 rev 1.2 SSD1331 there are fou r pha se s to driving an ole d a pixel. in pha se 1, the pixel is re set by the segme n t driver to v ls s in ord er to discha rg e the previo us d ata ch arg e st ored in th e parasiti c ca p acitan c e alo ng the segm ent elect r od e. the perio d of phase 1 ca n b e prog ra mme d by comma n d b1h a[3:0] from 1 to 15 dclk. an oled panel with larger cap acita n c e requi re s a longe r pe riod for disch argi n g. in phase 2, first pre - cha r g e is perform e d. the pixe l is driven to attain the correspondi ng voltage level v p fr om v lss . the a mplitude of v p can be p r og ramm ed by the com m and bbh. the pe riod of phase 2 can b e pro gra mmed in length fro m 1 to 15 dclk by com m and b1h a[7:4]. if the capacita n ce value of the pixel of oled p anel i s larger, a lon ger p e rio d is requi red to ch arg e up the capa citor to re ach the d e si red voltage. in phase 3, the oled pix e l is driven to the targeted dr iving voltag e throug h se con d pre - cha r ge. the se cond pre - cha r ge can control th e sp eed of the cha r gin g pro c e s s. the peri od of p h a se 3 can b e programme d by comm and s 8 a h, 8bh and 8ch. last pha se (pha se 4) is cu rre nt drive stage. the cu rre nt source in the segment driver delivers con s tant cu rre nt to the pixel. the driver ic emplo y s pulse widt h modulatio n (pwm ) meth od to control the gray scale of each pixel individually. t he wide r pul se widths in the cu rre nt dri v e stage re sults in bright er pixels an d vice versa. this is sh own in the followin g figure. fig u re 18 - gray scale control by pwm in segment after finishi n g phase 4, the driver ic will go back to ph ase 1 to displ a y the next row image data. this four-step cycle i s ru n continuo usly to refre s h im a ge display on oled pa nel. the le ngth of pha se 4 is d efined by co mmand b 8h ?set gr ay sca l e tabl e? or b 9h ?en able li nea r gray scale table ? . in the table, the gray scale is d efined in increm ent al way, with referen c e to the length o f previous tab l e entry. time segment voltage v lss oled panel wider puls e width drives pixel brighter phase1 phase2 phase3 phase4 v p
SSD1331 rev 1.2 p 27/68 nov 2007 s o l o mo n s y st ec h 7.9 pow er on and off sequence the followi ng figures illu strate the reco mmend ed po we r on and power off seque nce of ssd13 31 (a ssum e v dd and v ddio are at the sa me voltage le vel). powe r on se quen ce : 1. powe r on v dd , v ddio . 2. after v dd , v dd i o become stable, set res # pin lo w (lo gic lo w) for at least 3u s (t 1 ) and then hig h (logi c hig h). 3. after set res# pin lo w (lo g ic low), wait for at leas t 3us (t 2 ). then p owe r o n v cc. (1) 4. after v cc become sta b le, send comma n d afh for displa y on. seg/com will b e on after 1 0 0 ms (t af ). figure 19 : t he po w e r o n sequ e nc e powe r off seque nce : 1. send comma nd aeh for di splay off. 2. powe r off v cc. (1), (2) 3. wait for t off . powe r off v dd, v ddi o. (wh e re minimu m t off =0 ms, typical t off =100ms) figure 20 : t he po w e r of f sequen ce not e : (1) since an esd prote c tion circuit is con necte d betwe en v dd ,v ddi o and v cc , v cc become s lo wer than v dd whe neve r v dd ,v ddi o is on and v cc is off as sho w n in the dotted line of v cc in figure 19 an d figure 20 . (2) v cc should be ke pt float (disa b le ) wh e n it is off. off v dd ,v ddio v dd ,v dd i o v cc send comma nd aeh for di splay off off v cc gnd gnd t off gnd on v dd, v ddio res# on v cc send afh com m and for display on v dd, v ddio res# gnd t 1 seg/com t af on off v cc gnd t 2
solom on s y s t e c h nov 2007 p 28/68 rev 1.2 SSD1331 8 command tabl e ta ble 1 0 - comma nd ta ble funda me nta l comma nds d/c# hex d7 d6 d5 d4 d3 d2 d1 d0 comma nd de s c ription default 0 15 0 0 0 1 0 1 0 1 setup co lumn start and end a ddress 0 a[6:0] * a 6 a 5 a 4 a 3 a 2 a 1 a 0 a[6:0] start address from 00d- 95d 00d (00h) 0 b[6:0] * b 6 b 5 b 4 b 3 b 2 b 1 b 0 set colum n address b[6:0] end ad d r ess from 00d- 95d 95d (5f h ) 0 75 0 1 1 1 0 1 0 1 setup ro w sta r t and end addr ess 0 a[5:0] * * a 5 a 4 a 3 a 2 a 1 a 0 a[5:0] start address from 00d- 63d 00d (00h) 0 b[5:0] * * b 5 b 4 b 3 b 2 b 1 b 0 set ro w address b[5:0] end ad d r ess from 00d- 63d 63d (3f h ) 0 81 1 0 0 0 0 0 0 1 set contrast for all color "a " se gment (pins:sa0 ? s a 95) 0 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 set contrast for color "a" a[7:0] valid ran ge: 00d to 2 5 5 d 128 d (80h) 0 82 1 0 0 0 0 0 1 0 set contrast for all color "b " se gment (pins:sb0 ? s b95). 0 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 set contrast for color "b" a[7:0] valid ran ge: 00d to 2 5 5 d 128 d (80h) 0 83 1 0 0 0 0 0 1 1 set contrast for all color " c " se gment (pins:sc0 ? s c 95). 0 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 set contrast for color "c" a[7:0] valid ran ge: 00d to 2 5 5 d 128 d (80h) 0 87 1 0 0 0 0 1 1 1 0 a[3:0] 0 0 0 0 a 3 a 2 a 1 a 0 master current control set master current attenu atio n factor a[3:0] from 00d to 15d corres pon din g to 1/1 6 , 2/16? to 16/1 6 attenuati on. 15d (0f h )
SSD1331 rev 1.2 p 29/68 nov 2007 s o l o mo n s y st ec h funda me nta l comma nds d/c# hex d7 d6 d5 d4 d3 d2 d1 d0 comma nd description default 0 8a 1 0 0 0 1 0 1 0 a[7:0] of 81h 0 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 8b 1 0 0 0 1 0 1 1 a[7:0] of 82h 0 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 8c 1 0 0 0 1 1 0 0 a[7:0] of 83h 0 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 set second pre-charg e spee d for color ?a?, ?b? and ?c? a [7:0]: set second pre-c harg e spee d rang es: 000 00 00b to 11 11 11 1b, a hig her val ue of a[7:0] gives a hig her seco n d pre-charg e sp eed. note (1 ) t he default values of a[ 7:0] in 8ah, a[7:0] in 8bh a nd a[7 : 0] in 8ch are equ al to the contrast value s for color a, b and c( refer to commands: 81h, 82 h, 83h) respectiv e l y . (2 ) all si x b y t e s (8ah a[7:0], 8bh a[7:0] and 8ch a[7:0]) mu st be inputte d togeth e r. f o r exampl e: the o r igin al val ue is like that origina l valu e 8ah a[7:0]: 80h 8bh a[7:0]: 80h 8ch a[7:0]: 80h if it is w a nted t o chan ge the v a lue of 8bh a[7:0] to 75h, then a ll the foll o w i ng 6 b y t e s must be inp u tted: 8ah, 80 h, 8bh, 75 h, 8ch, 8 0h. 0 a0 1 0 1 0 0 0 0 0 set driver rem ap an d color d epth 0 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a[0]=0, horizontal address increment a[0]=0 a[0]= 1 , vertical address i n cre m ent a[1]= 0 , ram c o lumn 0 to 95 maps to pin se g (sa,sb,sc) 0 to 95 a[1]=0 a[1]= 1 , ram c o lumn 0 to 95 maps to pin se g (sa,sb,sc) 95 to 0 a[2]=0, normal order sa,sb,sc (e.g. rgb) a[2]=0 a[2]=1, reverse order sc,sb,sa (e.g. bgr) a[3]= 0 , disabl e left-right s w a ppin g on com a[3]= 0 a[3]= 1 , set left-right s w a p p in g on com a[4]= 0 , scan from com 0 to com [n ?1] a[4]= 0 a[4]=1, scan f rom com [n-1] to com0. where n is the multiple x rati o. a[5]= 0 , disable com split odd even (reset ) a[5]=0 a[5]= 1 , enable com split odd even a[7:6] = 00; 256 color format a[7:6] = 01; 65k color format a[7:6]= 0 1 a[7:6] = 10; 65k color format 2 remap & c o lo r depth settin g if 9 / 18 bit mo de is sel e cted, color d epth w i ll be fixed to 6 5 k regard l ess of the setting. 0 a1 1 0 1 0 0 0 0 1 set displ a y sta r t line regist er b y r o w 0 a[5:0] 0 0 a 5 a 4 a 3 a 2 a 1 a 0 set display start line a[5:0]: from 00d to 63d 00d (0 0h) 0 a2 1 0 1 0 0 0 1 0 set vertical offset b y c o m 0 a[5:0] 0 0 a 5 a 4 a 3 a 2 a 1 a 0 set display offset a[5:0]: from 00d to 63d 00d (0 0h)
solom on s y s t e c h nov 2007 p 30/68 rev 1.2 SSD1331 funda me nta l comma nds d/c# hex d7 d6 d5 d4 d3 d2 d1 d0 comma nd de s c ription default 0 a4 / 1 0 1 0 0 1 x 1 x 0 a4h=norma l di spla y a4h 0 a5 / a5h=entire dis play on, all pixels turn on at gs63 0 a6 / a6h=entire dis play off, all pix e ls turn off 0 a7 / set displ a y mode a7h= inverse d ispla y 0 a8 1 0 1 0 1 0 0 0 set mux rati o to n+ 1 mux 0 a[5:0] 0 0 a 5 a 4 a 3 a 2 a 1 a 0 n = a[5:0] from 15d to 63 d 63d (3fh) set multipl e x ratio a[5:0] from 00d to 14d ar e in valid en tr y 0 ab 1 0 1 0 1 0 1 1 0 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 b[7:0] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 c[7:0] c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 0 d[7:0] d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 e[4:0] 0 0 0 e 4 e 3 e 2 e 1 e 0 dim mode setting config ure d i m mode settin g a[7:0] = reserved. (set as 00h) b[7:0] = contrast setting for color a, vali d rang e 0 to 255 d. c[7:0] = contrast setting for color b, vali d rang e 0 to 255 d. d[7:0] = contrast setting for color c, val i d rang e 0 to 255 d. e[4:0] = prech a rge vo ltage s e tting, vali d rang e 0 to 31d. \ 0 ad 1 0 1 0 1 1 0 1 0 a[0] 1 0 0 0 1 1 1 a 0 a [ 0 ] = 1 set master config urati o n a[0]= 0b, select exter nal v cc s uppl y a[0]=1b, reser v ed (reset ) note (1 ) bit a[0] must be set to 0b after reset. (2 ) t he setting w i ll b e activate d after issuin g set displ a y o n command (a f h ) 0 ac 1 0 1 0 1 1 a 1 a 0 ach = displa y on in dim mod e ae aeh = displa y of f (sleep mode) aeh af af h = displa y on in normal mode set displ a y on/off 0 b0 1 0 1 1 0 0 0 0 0 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a[7:0]= 1 ah, enable p o w e r sa ve mode (reset ) 1ah po w e r sav e mode a[7:0]= 0 bh, disable p o w e r s a ve mod e 0 b1 1 0 1 1 0 0 0 1 a[3:0] phase 1 peri od in n d c lk. 1~ 15 dclk all o w e d . 74h 0 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 phase 1 a nd 2 perio d adjustm ent a[7:4] phase 2 peri od in n d c lk. 1~ 15 dclk al lo w e d note (1) 0 dclk is i n valid in pha se 1 & phase 2 0 b3 1 0 1 1 0 0 1 1 a[3:0]: define t he divi de rati o (d) of the d0h 0 a[7:0] a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 display c l ocks ( dclk): divid e ratio (d) = a[3:0] + 1 (i.e., 1 to 16) a[7:4] f o sc fre que nc y . displ a y clock divid er / oscillator f r eque nc y f r eque nc y incr eases as settin g valu e increas es
SSD1331 rev 1.2 p 31/68 nov 2007 s o l o mo n s y st ec h funda me nta l comma nds d/c# hex d7 d6 d5 d4 d3 d2 d1 d0 command description default 0 b8 1 0 1 1 1 0 0 0 \ 0 a[6:0] * a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 b[6:0] * b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 c[6:0] * c 6 c 5 c 4 c 3 c 2 c 1 c 0 0 ? ... ? ? ? ? ? ? ? 0 ae[6:0] * ae 6 ae 5 ae 4 ae 3 ae 2 ae 1 ae 0 0 af[6:0] * af 6 af 5 af 4 af 3 af 2 af 1 af 0 set gray scale t able t hese 32 para m eters defin e pulse w i dths of gs1 to gs63 in terms of dclk a[6:0]: pulse w i dth for gs1, reset=01d b[6:0]: pulse w i dth for gs3, reset=05d c[6:0]: pulse w i dth for gs5, reset=09d ? ae[6:0]: pulse w i dth for gs61 , reset = 121d af [6:0]: pulse w i dth for gs63 , reset = 125d note : (1) gs0 has n o pre-char ge a n d current drive stages. (2) gs2, gs4?gs62 are der iv ed b y pn = (pn-1+ pn+1 )/2 (3) pn w i ll be truncated to integer if it is w i th decima l poi nt. (4) pn+ 1 sh oul d al w a ys b e set to larger than pn-1 (5) ma x p u lse w idth is 12 5 0 b9 1 0 1 1 1 0 0 1 reset bu ilt in g r a y sca le tab l e (line a r) \ pulse w i dth for gs1 = 1d; pulse w i dth for gs2 = 3d; pulse w i dth for gs3 = 5d; ? pulse w i dth for gs61 = 121d; pulse w i dth for gs62 = 123d; enab le li near gra y scal e t able pulse w i dth for gs63 = 125d. 0 bb 1 0 1 1 1 0 1 1 set pre-char ge voltage l e vel. all three co lor share the sam e pre-ch arge v o ltag e. 3eh 0 a[5:0] 0 0 a 5 a 4 a 3 a 2 a 1 0 a[5:1] hex code pre-charge voltage 00000 00h 0.10 x v cc : : : 11111 3eh 0.50 x v cc set pre-charg e level refer to figure 30 for the d e tails setting of a[5:1]. 0 bc-bd 1 0 1 1 1 1 0 x 0 nop comman d for no op eratio n \ be 1 0 1 1 1 1 1 0 0 a[5:1] 0 0 a 5 a 4 a 3 a 2 a 1 0 set v comh set com desel ect voltage l e v e l (v comh ) a [ 5 : 1] hex co d e v comh 00000 00h 0.44 x v cc 01000 10h 0.52 x v cc 10000 20h 0.61 x v cc 11000 30h 0.71 x v cc 11111 3eh 0.83 x v cc 3eh 0 e3 1 1 1 0 0 0 1 1 nop comman d for no op eratio n \ 0 f d 1 1 1 1 1 1 0 1 0 a[2] 0 0 0 1 0 a 2 1 0 set command lock a[2]: mcu protection statu s a[2] = 0b, unl o ck ole d dri v er ic mcu interfa c e from enterin g com m and [re s et] a[2] = 1b, lock o l ed d r iver ic mcu interfa c e from enterin g com m and not e (1) the loc k ed oled driver ic mcu interfa c e proh ibits all co mm and s and memo ry acce ss ex cept the fdh comm and. 12h
solom on s y s t e c h nov 2007 p 32/68 rev 1.2 SSD1331 grap h i c a c cel eratio n co mman d s d/c# hex d7 d6 d5 d4 d3 d2 d1 d0 command desc ription 0 21 0 0 1 0 0 0 0 1 a[6:0]: column address of start 0 a[6:0] * a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[5:0]: ro w a ddress of start 0 b[5:0] * * b 5 b 4 b 3 b 2 b 1 b 0 c[6:0]: colum n address of e nd 0 c[6:0] * c 6 c 5 c 4 c 3 c 2 c 1 c 0 d[5:0]: ro w a ddress of end 0 d[5:0] * * d 5 d 4 d 3 d 2 d 1 d 0 e[5:1]: color c of the line 0 e[5:1] * * e 5 e 4 e 3 e 2 e 1 * f [ 5:0]: color b of the line 0 f [ 5:0] * * f 5 f 4 f 3 f 2 f 1 f 0 g[5:1]: color a of the line 0 g[5:1] * * g 5 g 4 g 3 g 2 g 1 * dra w li ne 0 22 0 0 1 0 0 0 1 0 a[6:0]: column address of start 0 a[6:0] * a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[5:0]: ro w a ddress of start 0 b[5:0] * * b 5 b 4 b 3 b 2 b 1 b 0 c[6:0]: colum n address of e nd 0 c[6:0] * c 6 c 5 c 4 c 3 c 2 c 1 c 0 d[5:0]: ro w a ddress of end 0 d[5:0] * * d 5 d 4 d 3 d 2 d 1 d 0 e[5:1]: color c of the line 0 e[5:1] * * e 5 e 4 e 3 e 2 e 1 * f [ 5:0]: color b of the line 0 f [ 5:0] * * f 5 f 4 f 3 f 2 f 1 f 0 g[5:1]: color a of the line 0 g[5:1] * * g 5 g 4 g 3 g 2 g 1 * h[5:1]: color c of the fill are a 0 h[5:1] * * h 5 h 4 h 3 h 2 h 1 * i[5:0]: color b of the fill area 0 i[5:0] * * i 5 i 4 i 3 i 2 i 1 i0 j[5:1]: color a of the fill area 0 j[5:1] * * j 5 j 4 j 3 j 2 j 1 * dra w i ng rectan gle 0 23 0 0 1 0 0 0 1 1 a[6:0]: column address of s t art 0 a[6:0] * a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[5:0]: ro w a ddress of start 0 b[5:0] * * b 5 b 4 b 3 b 2 b 1 b 0 c[6:0]: colum n address of e nd 0 c[6:0] * c 6 c 5 c 4 c 3 c 2 c 1 c 0 d[5:0]: ro w a ddress of end 0 d[5:0] * * d 5 d 4 d 3 d 2 d 1 d 0 e[6:0]: column address of new start 0 e[6:0] * e 6 e 5 e 4 e 3 e 2 e 1 e 0 f [ 5:0]: ro w a ddress of ne w start 0 f [ 5:0] * * f 5 f 4 f 3 f 2 f 1 f 0 cop y 0 24 0 0 1 0 0 1 0 0 a[6:0]: column address of start 0 a[6:0] * a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[5:0]: ro w a ddress of start 0 b[5:0] * * b 5 b 4 b 3 b 2 b 1 b 0 c[6:0]: colum n address of e nd 0 c[6:0] * c 6 c 5 c 4 c 3 c 2 c 1 c 0 d[5:0]: ro w a ddress of end 0 d[5:0] * * d 5 d 4 d 3 d 2 d 1 d 0 t he effect of dim w i ndo w : gs15~gs0 no change gs19~gs16 become gs4 gs23~gs20 become gs5 ... dim windo w gs63~ gs60 become gs15 0 25 0 0 1 0 0 1 0 1 a[6:0]: column address of start 0 a[6:0] * a 6 a 5 a 4 a 3 a 2 a 1 a 0 b[5:0]: ro w a ddress of start 0 b[5:0] * * b 5 b 4 b 3 b 2 b 1 b 0 c[6:0]: colum n address of e nd 0 c[6:0] * c 6 c 5 c 4 c 3 c 2 c 1 c 0 d[5:0]: ro w a ddress of end 0 d[5:0] * * d 5 d 4 d 3 d 2 d 1 d 0 clear w i n d o w 0 26 0 0 1 0 0 1 1 0 a0 0 : disable fill for dra w r e ctan gle command (re set ) 0 a[4:0] * * * a 4 0 0 0 a 0 1 : enable fill for dra w r e ctan gle command a[3:1] 000: re served va lues a4 0 : disable rev e rse copy (reset ) fill enab le / disab le 1 : enable rev e rse dur ing co p y command.
SSD1331 rev 1.2 p 33/68 nov 2007 s o l o mo n s y st ec h grap h i c a c cel eratio n co mman d s d/c# hex d7 d6 d5 d4 d3 d2 d1 d0 command desc ription 0 27 0 0 1 0 0 1 1 1 a[6:0]: set number of colum n as horiz ontal scroll offset 0 a[6:0] * a 6 a 5 a 4 a 3 a 2 a 1 a 0 rang e: 0d-9 5 d ( no horizo n tal scroll if equ als to 0) 0 b[5:0] * * b 5 b 4 b 3 b 2 b 1 b 0 b[5:0]: define start ro w a ddre ss 0 c[6:0] * c 6 c 5 c 4 c 3 c 2 c 1 c 0 c[6:0]: set number of ro w s to be hor izonta l scrolled b[5:0]+ c [6:0] <=64 0 d[5:0] * * d 5 d 4 d 3 d 2 d 1 d 0 d[5:0]: set number of row as vertical scroll offset rang e: 0d-6 3 d ( no vertical sc roll if equ als to 0) 0 e[1:0] * * * * * * e 1 e 0 contin uo us horizo ntal & vertical scrolling setup e[1:0]: set time interva l bet w een e a ch scrol l step 00b 6 frames 01b 10 frame s 10b 100 fram es 11b 200 fram es note : (1) vertic al scr oll is run w i t h 6 4 mu x setting onl y (2) t he param eters shou ld n o t be chan ge d after scrollin g i s activated 0 2e 0 0 1 0 1 1 1 0 deactivat e scrolli ng t h is command deactivates th e scrolli ng action. note (1) after sen d i ng 2eh comm a nd to deactiv a t e the scrolli ng ac tion, the ram d a ta nee ds to b e re w ritten. 0 2f 0 0 1 0 1 1 1 1 activate scrolli ng t h is command activates the scrolli ng functi o n accordi ng to th e setting do ne b y c onti nuo us horizo ntal & v e rtical scrol lin g setup command 27h.
solom on s y s t e c h nov 2007 p 34/68 rev 1.2 SSD1331 8.1 data read / write to re ad data from the g d dram, in put high to r/w#(wr# )# pin and d/c# pi n for 68 00-se rie s pa rallel mode , low to e (rd# ) pin and high to d/c# pin for 808 0-seri es p aral l el mode. no data rea d is provid ed in serial mode o peration. in norm a l dat a rea d mo de , gddram column a d d r e ss pointe r wil l be incre a se d by one a u tomatically after each data rea d . also, a dumm y read is requ ired b e fore th e first data re ad. to write d a ta to the gddram, input l o w to r/w#(wr# ) pin a n d high to d/ c# pin for 6 8 00-se rie s parallel mode and 8 080 -serie s pa rallel mo de. for se rial inte rface mo de, it is always in write mode. g d dram colu mn address point e r will be incr eased by one automatically after each data write. t a b l e 11 - a d d r ess in cre m e n t tab l e ( a u t o m atic) d/c# r/w#(wr#) comment address increme nt 0 0 write command no 0 1 read status no 1 0 write data yes 1 1 read data y es
SSD1331 rev 1.2 p 35/68 nov 2007 s o l o mo n s y st ec h 9 command des cri ptions 9.1 fundamental command 9.1.1 set column address (1 5 h ) this comm an d spe c ifie s co lumn sta r t ad dre s s and e n d add re ss of the displ ay d ata ram. thi s co mman d a l so s e ts the c o lumn address pointer to c o lumn s t art address . this pointer is used to define the current re ad/write colu mn add re ss in graphi c displ ay data ram. if horiz ontal ad dress increme n t mode is en ab led by comm and a0h, after finishin g rea d /write one colu mn data, it is increm ented automaticall y to the next colu mn add ress. whe neve r th e col umn ad dre s s poi nter finishe s a ccessing th e e nd colum n a ddress, it is reset b a ck to start colu mn ad dre ss. 9.1.2 set ro w address (75h ) this com m an d sp ecifie s row start ad dress an d en d add re ss of the display dat a ram. thi s comm and al so sets the ro w add re ss poi nter to row sta r t addre ss. this pointe r is used to define the curren t read/write row add re ss i n graphi c di splay data ram. if vertical a dd r ess in cremen t mode is en abled by co m m and a0 h, after finishin g rea d / write one ro w data, it is increme nted autom ati c ally to the next row add re ss. whe neve r the row add re ss p oint er finishe s acce ssi ng the e nd ro w ad dre ss, it is re set back t o st a r t row ad dr es s. the figu re b e l ow sho w s th e way of col u mn an d ro w add re ss point er move ment throu gh the example: col umn start add re ss is set to 2 and colu mn e nd add re ss i s set to 93, row sta r t address is set to 1 and row e nd add re ss i s set to 62. ho rizontal a ddress in cremen t mode i s en abled by co mmand a 0h. in this ca se, the gra phi c displ ay data ram column a c ce ssi ble ra nge i s from colum n 2 to colum n 93 and fro m row 1 to ro w 62 only. in addi tion, the colu mn add re ss pointe r is set to 2 and row address p o i n ter is set to 1. after finishing rea d/write on e pixel of data, the colum n address is increa se d au tomatically b y 1 to acce ss the next ram locatio n for n ext read/ write ope ration ( solid line i n figure 21 ). wh eneve r the column add re ss poi nter fini shes acce ssi ng th e end colu m n 93, it is re set back to co lumn 2 a nd row a ddress i s autom atical ly incre a sed by 1 ( solid line in figure 21 ). while th e en d ro w 62 and e nd column 93 ram lo catio n is a c ce ssed , the ro w ad dress is res e t back to 1 ( dotted li ne in figu re 2 1 ). col 0 col 1 col 2 ?.. ??. col 93 col 94 col 95 r o w 0 r o w 1 r o w 2 : : : : : : r o w 6 1 r o w 6 2 r o w 6 3 figure 2 1 - ex a m ple of colu mn a nd ro w a d dres s pointe r mo v e me nt
solom on s y s t e c h nov 2007 p 36/68 rev 1.2 SSD1331 9.1.3 set contras t for color a, b, c (81h, 82h, 83h) this co mman d is to set contra st setting of each col or a, b and c. the chip ha s three co ntra st control circui ts for col or a, b and c. ea ch contrast circuit has 25 6 co ntra st st eps from 00 h to ffh. the se gment o utput cu rre nt i seg incr ea se s wit h t he co nt ra st st ep, whi c h results in bri ghte r of the colo r. 9.1.4 master curr ent control (87h) this comma n d is to control the segment output cu rren t by a s c a ling fac t or. this fac t or is common to c o lor a, b and c. the chip has 16 m aster control steps. the fa ctor i s ranged from 1 [0000b] to 16 [1111b]. reset is 16 [1111b]. the smaller the maste r cu rre nt value, the dimme r the oled pa nel displ ay is set. for exampl e, if origi nal se gm ent output cu rre nt of a co lor is 160 ua at scale facto r = 16, se tting scale facto r to 8 to reduce th e cu rre nt to 80ua.
SSD1331 rev 1.2 p 37/68 nov 2007 s o l o mo n s y st ec h 9.1.5 set second pre-charge speed for color a, b, c (8ah) the valu e set sho u ld m a tch with th e co ntra st of the colo r a, b, c. an initial trial should be the value sam e as the co ntra st a, b, c. wh en fa ste r spe ed is ne ede d, highe r valu e can be set a n d vice ve rsa. figure 22 sh ows the effect of setting se con d pre-ch arge u nde r differ ent spee ds th rou gh usi ng com m and 8ah, 8 b h and 8 c h. figu re 2 2 - effe c t of s e tting the s e c ond p r e - c h a r g e unde r diffe re nt s p e e d s 9.1.6 set re-map & data for mat (a0h) this comm an d has m u ltipl e config uratio ns an d ea ch bit setting is d e scri bed a s follows. ? addre s s incre m ent mode (a[0]) whe n it is set to 0, the driver is set as hori z o n tal ad dre s s increm ent mode. after the displa y ram is rea d /written, the colum n a ddress point er is incr e a sed automati c ally by 1. if the column add re ss pointer rea c h es colum n en d add re ss, th e colu mn ad d r e ss p ointer i s re set to col umn sta r t add re ss a nd ro w address pointe r is increased by 1. the se que nce of movement of the row and col umn add re ss point for ho rizontal add re ss increment m ode is sho w n in figure 23. f i g u r e 23 - a d d r ess po in ter mo v e ment o f ho rizo n tal a d d r ess in cre m e n t mo d e col 0 col 1 ?.. col 94 col 95 ro w 0 ro w 1 : : : : : : ro w 62 ro w 63 whe n a[0] is set to 1, the driver i s set to vertic al ad d r e ss in creme n t mode. after the display ram is rea d/written, the ro w a ddress poi nt er i s in crea sed automati c ally by 1. if th e ro w a ddre ss pointe r rea c h es the ro w end add re ss, the ro w addre s s poi nter is re set to row sta r t add re ss an d column add re ss p oint er is in crea se d by 1. the seq uen ce of movement of the ro w and column a dd r e s s point for vertical a d d re ss increm ent mode i s shown in figu re 24. f i g u r e 24 - a d d r ess po in ter mo v e men t o f vertical a d d r e ss in crem en t mo d e col 0 col 1 ?.. col 94 col 95 ro w 0 ?.. ro w 1 ?.. : : ro w 62 ?.. ro w 63 ?.. segment voltage phase1 phase2 phase4 v p different s e ttings in second pre-ch arg e speed ... seco nd pre - charge spe ed = 1 seco nd pre - charge spee d = 255 v lss phase3 time
solom on s y s t e c h nov 2007 p 38/68 rev 1.2 SSD1331 ? colu mn add r ess map p ing (a[1]) this comm an d bit is made for flexible layout of segm e n t signal s in oled mo dul e with se gme n t arrang ed fro m left to right or vice versa. the displ a y dire ction i s either ma ppin g displ a y data ram colu mn 0 to seg0 pin (a[1] = 0), or ma p p ing di splay d a ta ram col u mn 95 to seg0 pin (a[1] = 1). the effect s of both are sho w n in figure 25. figure 2 5 - ex a m ple of colu mn a ddre s s ma pping ? rgb mapping (a[2]) this com m a nd bit is ma de for flexibl e layout of segme n t sig n a ls in ole d modul e to match filter desi gn. ? com left / right remap (a[3]) this com m a nd bit i s ma de for flexibl e layout of comm on sig nals i n o led mo dule wi th com 0 arrang ed on either left or right side. de tails of pin arrange ment ca n be found in table 12 an d figure 26. ? com scan di re ction rema p (a[4]) this bit dete r mine s the scannin g di re ction of the co mmon fo r fle x ible layout o f comm on si gnal s in oled mod u l e either from up to down or vice ve rsa. details of pin arra nge ment can be found in table 12 and figure 26. ? odd even sp lit of com pin s (a[5]) this bit can set the odd even arran gem ent of com p ins. a[5] = 0: disa ble co m split odd even, pi n as sign ment of common i s in se que ntial as com63 com62 .... com 33 com32..sc 95..sa0..com0 com1.... com30 com31 a[5] = 1: ena b le co m split odd even, pi n as sign ment of common i s in odd eve n split as com63 com61.... com3 com1..sc95 ..sa0..com0 com2.... com60 com62 detail s of pin arrang eme n t can b e found in table 1 2 a nd figu re 26. ? display col o r mode (a[7:6]) select eith er 65k or 256 color m ode. t he di splay ram data form at in differe nt mode i s d e scri bed i n se ct ion 7.5 SSD1331 sa0 sb0 sc0 sa95 sb95 sc95 SSD1331 sa0 sb0 sc0 sa95 sb95 sc95 colu mn 0 ma ps to seg0 p in colu mn 95 m aps to seg0 pin ?????? ??????
SSD1331 rev 1.2 p 39/68 nov 2007 s o l o mo n s y st ec h ta ble 1 2 - ill u s tra t ion of d i ff e r e n t com ou tput s e ttings case a c ase b c ase c c ase d c ase e c ase f c ase g c ase h a [ 5: 3]=000 a [ 5: 3]=001 a [ 5: 3]=010 a [ 5: 3]=011 a [ 5: 3]=100 a [ 5: 3]=101 a [ 5: 3]= 110 a [ 5: 3]=111 i c pa d no . p in nam e 195 com 0 r ow 0 r ow 3 2 r ow 6 3 r ow 3 1 r ow 0 r ow 1 r ow 6 3 r ow 6 2 194 com 1 r ow 1 r ow 3 3 r ow 6 2 r ow 3 0 r ow 2 r ow 3 r ow 6 1 r ow 6 0 193 com 2 r ow 2 r ow 3 4 r ow 6 1 r ow 2 9 r ow 4 r ow 5 r ow 5 9 r ow 5 8 192 com 3 r ow 3 r ow 3 5 r ow 6 0 r ow 2 8 r ow 6 r ow 7 r ow 5 7 r ow 5 6 191 com 4 r ow 4 r ow 3 6 r ow 5 9 r ow 2 7 r ow 8 r ow 9 r ow 5 5 r ow 5 4 190 com 5 ro w 5 ro w 3 7 r o w 58 ro w 2 6 r o w 10 ro w 1 1 r o w 53 ro w 5 2 ??? ?????? ? 169 com 26 r ow 2 6 r ow 5 8 r ow 3 7 r ow 5 r ow 5 2 r ow 5 3 r ow 1 1 r ow 1 0 168 com 27 r ow 2 7 r ow 5 9 r ow 3 6 r ow 4 r ow 5 4 r ow 5 5 r o w 9 r ow 8 167 com 28 r ow 2 8 r ow 6 0 r ow 3 5 r ow 3 r ow 5 6 r ow 5 7 r o w 7 r ow 6 166 com 29 r ow 2 9 r ow 6 1 r ow 3 4 r ow 2 r ow 5 8 r ow 5 9 r o w 5 r ow 4 165 com 30 r ow 3 0 r ow 6 2 r ow 3 3 r ow 1 r ow 6 0 r ow 6 1 r o w 3 r ow 2 164 com 31 r ow 3 1 r ow 6 3 r ow 3 2 r ow 0 r ow 6 2 r ow 6 3 r o w 1 r ow 0 488 com 32 r ow 3 2 r ow 0 r ow 3 1 r ow 6 3 r ow 1 r ow 0 r ow 6 2 r ow 6 3 489 com 33 r ow 3 3 r ow 1 r ow 3 0 r ow 6 2 r ow 3 r ow 2 r ow 6 0 r ow 6 1 490 com 34 r ow 3 4 r ow 2 r ow 2 9 r ow 6 1 r ow 5 r ow 4 r ow 5 8 r ow 5 9 491 com 35 r ow 3 5 r ow 3 r ow 2 8 r ow 6 0 r ow 7 r ow 6 r ow 5 6 r ow 5 7 492 com 36 r ow 3 6 r ow 4 r ow 2 7 r ow 5 9 r ow 9 r ow 8 r ow 5 4 r ow 5 5 493 com 37 r ow 3 7 r ow 5 r ow 2 6 r ow 5 8 r ow 1 1 r ow 1 0 r ow 5 2 r ow 5 3 ??? ?????? ? 514 com 58 ro w 5 8 r o w 26 ro w 5 ro w 3 7 r o w 53 ro w 5 2 r o w 10 ro w 1 1 515 com 59 ro w 5 9 r o w 27 ro w 4 ro w 3 6 r o w 55 ro w 5 4 r o w 8 r o w 9 516 com 60 ro w 6 0 r o w 28 ro w 3 ro w 3 5 r o w 57 ro w 5 6 r o w 6 r o w 7 517 com 61 ro w 6 1 r o w 29 ro w 2 ro w 3 4 r o w 59 ro w 5 8 r o w 4 r o w 5 518 com 62 ro w 6 2 r o w 30 ro w 1 ro w 3 3 r o w 61 ro w 6 0 r o w 2 r o w 3 519 com 63 ro w 6 3 r o w 31 ro w 0 ro w 3 2 r o w 63 ro w 6 2 r o w 0 r o w 1 o u tput s ig n al
solom on s y s t e c h nov 2007 p 40/68 rev 1.2 SSD1331 figure 2 6 - c o m pins ha rd w a re confi gur a tion (mux ra tio: 6 4 ) cas e and co nditions com pins configura t ion s a a[5] =0 a[4]=0 a[3]=0 disable o dd even split of com pi ns com scan directio n: from com0 to com63 disable com left / right remap b a[5] =0 a[4]=0 a[3]=1 disable o dd even split of com pi ns com scan directio n: from com0 to com63 enable com left / right remap c a[5] =0 a[4]=1 a[3]=0 disable o dd even split of com pi ns com scan directio n: from com 63 to com0 disable com left / right remap 96 x 64 row0 row31 row32 row63 pad 1,2,3,?->16 3 gold b ump s f ace u p SSD1331z com0 com31 com32 com63 96 x 64 row32 row63 row0 row31 pad 1,2,3,?->16 3 gold b ump s f ace u p SSD1331z com0 com31 com63 com32 96 x 64 row63 row32 row31 row0 pad 1,2,3,?->16 3 gold b ump s f ace u p SSD1331z com0 com31 com32 com63
SSD1331 rev 1.2 p 41/68 nov 2007 s o l o mo n s y st ec h cas e and co nditions com pins configura t ion s d a[5] =0 a[4]=1 a[3]=1 disable o dd even split of com pi ns com scan directio n: from com 63 to com0 enable com left / right remap e a[5] =1 a[4]=0 a[3]=0 enable o dd even split of com pins com scan directio n: from com0 to com63 disable com left / right remap f a[5] =1 a[4]=0 a[3]=1 enable o dd even split of com pins com scan directio n: from com0 to com63 enable com left / right remap 96 x 64 row0 row62 row1 row63 pad 1,2,3,?->16 3 gold b ump s f ace u p SSD1331z com0 com31 com32 com63 row61 com62 row2 com1 96 x 64 row31 row0 row63 row32 pad 1,2,3,?->16 3 gold b ump s f ace u p SSD1331z com0 com31 com63 com32 96 x 64 row0 row62 row1 row63 pad 1,2,3,?->16 3 gold b ump s f ace u p SSD1331z com0 com31 com32 com63 row61 com33 row2 com30
solom on s y s t e c h nov 2007 p 42/68 rev 1.2 SSD1331 cas e and co nditions com pins configura t ion s g a[5] =1 a[4]=1 a[3]=0 enable o dd even split of com pins com scan directio n: from com 63 to com0 disable com left / right remap h a[5] =1 a[4]=1 a[3]=1 enable o dd even split of com pins com scan directio n: from com 63 to com0 enable com left / right remap 9.1.7 set displa y start line (a1h) this comm a nd is to set display start line re gist e r to determin e startin g ad dre s s of disp lay ram to be displ a yed by sele cting a value from 0 to 63. table 13 and table 14 sho w example s of this com m an d. in there, ?ro w ? mean s the graphi c display data ram ro w. 9.1.8 set displa y offse t (a2h) this com m an d sp ecifie s th e map p ing of displ a y sta r t line (it i s a s sumed th at com0 i s the d i splay start li ne, displ ay start line regi ster e qual s to 0) to one of com 0 -6 3. for example, to move the com1 6 towards th e com 0 dire cti on for 16 line s , the 6-bit d a ta in the se con d com m a nd sh ould b e given by 001000 0b. tabl e 13 and table 14 sho w exam pl es of this co mmand. in there, ?ro w ? m ean s the grap hic di splay da ta ram ro w. 96 x 64 row63 row1 row62 row0 pad 1,2,3,?->16 3 gold b ump s f ace u p SSD1331z com0 com31 com32 com63 row2 com62 row61 com1 96 x 64 row63 row1 row62 row0 pad 1,2,3,?->16 3 gold b ump s f ace u p SSD1331z com0 com31 com32 com63 row2 com33 row61 com30
SSD1331 rev 1.2 p 43/68 nov 2007 s o l o mo n s y st ec h t a b l e 13 - examp l e o f set disp la y offset a n d disp lay start l i n e w i th no remap s e t m u x r a t i o( a 8h) c o m s c an dir ec t ion r em ap ( a 0h a [ 4] ) d i s pl ay off s et ( a 2h) d i s p l a y s t ar t l i ne ( a 1h) co m0 r o w 0 ra m 0 r o w 8 r a m8 ro w0 r a m8 ro w0 r a m0 r o w 8 ra m 8 r o w 0 ra m 8 co m1 r o w 1 ra m 1 r o w 9 r a m9 ro w1 r a m9 ro w1 r a m1 r o w 9 ra m 9 r o w 1 ra m 9 c o m 2 row 2 r a m2 row 10 r a m 10 r ow 2 r a m10 r ow 2 r a m 2 r ow 10 ra m 10 r ow 2 r a m 10 c o m 3 row 3 r a m3 row 11 r a m 11 r ow 3 r a m11 r ow 3 r a m 3 r ow 11 ra m 11 r ow 3 r a m 11 c o m 4 row 4 r a m4 row 12 r a m 12 r ow 4 r a m12 r ow 4 r a m 4 r ow 12 ra m 12 r ow 4 r a m 12 c o m 5 row 5 r a m5 row 13 r a m 13 r ow 5 r a m13 r ow 5 r a m 5 r ow 13 ra m 13 r ow 5 r a m 13 c o m 6 row 6 r a m6 row 14 r a m 14 r ow 6 r a m14 r ow 6 r a m 6 r ow 14 ra m 14 r ow 6 r a m 14 c o m 7 row 7 r a m7 row 15 r a m 15 r ow 7 r a m15 r ow 7 r a m 7 r ow 15 ra m 15 r ow 7 r a m 15 c o m 8 row 8 r a m8 row 16 r a m 16 r ow 8 r a m16 r ow 8 r a m 8 r ow 16 ra m 16 r ow 8 r a m 16 c o m 9 row 9 r a m9 row 17 r a m 17 r ow 9 r a m17 r ow 9 r a m 9 r ow 17 ra m 17 r ow 9 r a m 17 co m 1 0 r ow 10 ra m 1 0 r ow 18 r a m18 r ow 10 r a m18 r ow 10 ra m 1 0 r ow 18 ra m 1 8 r ow 10 ra m 1 8 co m 1 1 r ow 11 ra m 1 1 r ow 19 r a m19 r ow 11 r a m19 r ow 11 ra m 1 1 r ow 19 ra m 1 9 r ow 11 ra m 1 9 co m 1 2 r ow 12 ra m 1 2 r ow 20 r a m20 r ow 12 r a m20 r ow 12 ra m 1 2 r ow 20 ra m 2 0 r ow 12 ra m 2 0 co m 1 3 r ow 13 ra m 1 3 r ow 21 r a m21 r ow 13 r a m21 r ow 13 ra m 1 3 r ow 21 ra m 2 1 r ow 13 ra m 2 1 co m 1 4 r ow 14 ra m 1 4 r ow 22 r a m22 r ow 14 r a m22 r ow 14 ra m 1 4 r ow 22 ra m 2 2 r ow 14 ra m 2 2 co m 1 5 r ow 15 ra m 1 5 r ow 23 r a m23 r ow 15 r a m23 r ow 15 ra m 1 5 r ow 23 ra m 2 3 r ow 15 ra m 2 3 co m 1 6 r ow 16 ra m 1 6 r ow 24 r a m24 r ow 16 r a m24 r ow 16 ra m 1 6 r ow 24 ra m 2 4 r ow 16 ra m 2 4 co m 1 7 r ow 17 ra m 1 7 r ow 25 r a m25 r ow 17 r a m25 r ow 17 ra m 1 7 r ow 25 ra m 2 5 r ow 17 ra m 2 5 co m 1 8 r ow 18 ra m 1 8 r ow 26 r a m26 r ow 18 r a m26 r ow 18 ra m 1 8 r ow 26 ra m 2 6 r ow 18 ra m 2 6 co m 1 9 r ow 19 ra m 1 9 r ow 27 r a m27 r ow 19 r a m27 r ow 19 ra m 1 9 r ow 27 ra m 2 7 r ow 19 ra m 2 7 co m 2 0 r ow 20 ra m 2 0 r ow 28 r a m28 r ow 20 r a m28 r ow 20 ra m 2 0 r ow 28 ra m 2 8 r ow 20 ra m 2 8 co m 2 1 r ow 21 ra m 2 1 r ow 29 r a m29 r ow 21 r a m29 r ow 21 ra m 2 1 r ow 29 ra m 2 9 r ow 21 ra m 2 9 co m 2 2 r ow 22 ra m 2 2 r ow 30 r a m30 r ow 22 r a m30 r ow 22 ra m 2 2 r ow 30 ra m 3 0 r ow 22 ra m 3 0 co m 2 3 r ow 23 ra m 2 3 r ow 31 r a m31 r ow 23 r a m31 r ow 23 ra m 2 3 r ow 31 ra m 3 1 r ow 23 ra m 3 1 co m 2 4 r ow 24 ra m 2 4 r ow 32 r a m32 r ow 24 r a m32 r ow 24 ra m 2 4 r ow 32 ra m 3 2 r ow 24 ra m 3 2 co m 2 5 r ow 25 ra m 2 5 r ow 33 r a m33 r ow 25 r a m33 r ow 25 ra m 2 5 r ow 33 ra m 3 3 r ow 25 ra m 3 3 co m 2 6 r ow 26 ra m 2 6 r ow 34 r a m34 r ow 26 r a m34 r ow 26 ra m 2 6 r ow 34 ra m 3 4 r ow 26 ra m 3 4 co m 2 7 r ow 27 ra m 2 7 r ow 35 r a m35 r ow 27 r a m35 r ow 27 ra m 2 7 r ow 35 ra m 3 5 r ow 27 ra m 3 5 co m 2 8 r ow 28 ra m 2 8 r ow 36 r a m36 r ow 28 r a m36 r ow 28 ra m 2 8 r ow 36 ra m 3 6 r ow 28 ra m 3 6 co m 2 9 r ow 29 ra m 2 9 r ow 37 r a m37 r ow 29 r a m37 r ow 29 ra m 2 9 r ow 37 ra m 3 7 r ow 29 ra m 3 7 co m 3 0 r ow 30 ra m 3 0 r ow 38 r a m38 r ow 30 r a m38 r ow 30 ra m 3 0 r ow 38 ra m 3 8 r ow 30 ra m 3 8 co m 3 1 r ow 31 ra m 3 1 r ow 39 r a m39 r ow 31 r a m39 r ow 31 ra m 3 1 r ow 39 ra m 3 9 r ow 31 ra m 3 9 co m 3 2 r ow 32 ra m 3 2 r ow 40 r a m40 r ow 32 r a m40 r ow 32 ra m 3 2 r ow 40 ra m 4 0 r ow 32 ra m 4 0 co m 3 3 r ow 33 ra m 3 3 r ow 41 r a m41 r ow 33 r a m41 r ow 33 ra m 3 3 r ow 41 ra m 4 1 r ow 33 ra m 4 1 co m 3 4 r ow 34 ra m 3 4 r ow 42 r a m42 r ow 34 r a m42 r ow 34 ra m 3 4 r ow 42 ra m 4 2 r ow 34 ra m 4 2 co m 3 5 r ow 35 ra m 3 5 r ow 43 r a m43 r ow 35 r a m43 r ow 35 ra m 3 5 r ow 43 ra m 4 3 r ow 35 ra m 4 3 co m 3 6 r ow 36 ra m 3 6 r ow 44 r a m44 r ow 36 r a m44 r ow 36 ra m 3 6 r ow 44 ra m 4 4 r ow 36 ra m 4 4 co m 3 7 r ow 37 ra m 3 7 r ow 45 r a m45 r ow 37 r a m45 r ow 37 ra m 3 7 r ow 45 ra m 4 5 r ow 37 ra m 4 5 co m 3 8 r ow 38 ra m 3 8 r ow 46 r a m46 r ow 38 r a m46 r ow 38 ra m 3 8 r ow 46 ra m 4 6 r ow 38 ra m 4 6 co m 3 9 r ow 39 ra m 3 9 r ow 47 r a m47 r ow 39 r a m47 r ow 39 ra m 3 9 r ow 47 ra m 4 7 r ow 39 ra m 4 7 co m 4 0 r ow 40 ra m 4 0 r ow 48 r a m48 r ow 40 r a m48 r ow 40 ra m 4 0 r ow 48 ra m 4 8 r ow 40 ra m 4 8 co m 4 1 r ow 41 ra m 4 1 r ow 49 r a m49 r ow 41 r a m49 r ow 41 ra m 4 1 r ow 49 ra m 4 9 r ow 41 ra m 4 9 co m 4 2 r ow 42 ra m 4 2 r ow 50 r a m50 r ow 42 r a m50 r ow 42 ra m 4 2 r ow 50 ra m 5 0 r ow 42 ra m 5 0 co m 4 3 r ow 43 ra m 4 3 r ow 51 r a m51 r ow 43 r a m51 r ow 43 ra m 4 3 r ow 51 ra m 5 1 r ow 43 ra m 5 1 co m 4 4 r ow 44 ra m 4 4 r ow 52 r a m52 r ow 44 r a m52 r ow 44 ra m 4 4 r ow 52 ra m 5 2 r ow 44 ra m 5 2 co m 4 5 r ow 45 ra m 4 5 r ow 53 r a m53 r ow 45 r a m53 r ow 45 ra m 4 5 r ow 53 ra m 5 3 r ow 45 ra m 5 3 co m 4 6 r ow 46 ra m 4 6 r ow 54 r a m54 r ow 46 r a m54 r ow 46 ra m 4 6 r ow 54 ra m 5 4 r ow 46 ra m 5 4 co m 4 7 r ow 47 ra m 4 7 r ow 55 r a m55 r ow 47 r a m55 r ow 47 ra m 4 7 r ow 55 ra m 5 5 r ow 47 ra m 5 5 co m 4 8 r ow 48 ra m 4 8 r ow 56 r a m56 r ow 48 r a m56 r ow 48 ra m 4 8 - - r ow 48 ra m 5 6 co m 4 9 r ow 49 ra m 4 9 r ow 57 r a m57 r ow 49 r a m57 r ow 49 ra m 4 9 - - r ow 49 ra m 5 7 co m 5 0 r ow 50 ra m 5 0 r ow 58 r a m58 r ow 50 r a m58 r ow 50 ra m 5 0 - - r ow 50 ra m 5 8 co m 5 1 r ow 51 ra m 5 1 r ow 59 r a m59 r ow 51 r a m59 r ow 51 ra m 5 1 - - r ow 51 ra m 5 9 co m 5 2 r ow 52 ra m 5 2 r ow 60 r a m60 r ow 52 r a m60 r ow 52 ra m 5 2 - - r ow 52 ra m 6 0 co m 5 3 r ow 53 ra m 5 3 r ow 61 r a m61 r ow 53 r a m61 r ow 53 ra m 5 3 - - r ow 53 ra m 6 1 co m 5 4 r ow 54 ra m 5 4 r ow 62 r a m62 r ow 54 r a m62 r ow 54 ra m 5 4 - - r ow 54 ra m 6 2 co m 5 5 r ow 55 ra m 5 5 r ow 63 r a m63 r ow 55 r a m63 r ow 55 ra m 5 5 - - r ow 55 ra m 6 3 co m 5 6 r ow 56 ra m 5 6 r ow 0 r a m 0 r ow 56 ra m 0 - - row 0 r a m0 - - co m 5 7 r ow 57 ra m 5 7 r ow 1 r a m 1 r ow 57 ra m 1 - - row 1 r a m1 - - co m 5 8 r ow 58 ra m 5 8 r ow 2 r a m 2 r ow 58 ra m 2 - - row 2 r a m2 - - co m 5 9 r ow 59 ra m 5 9 r ow 3 r a m 3 r ow 59 ra m 3 - - row 3 r a m3 - - co m 6 0 r ow 60 ra m 6 0 r ow 4 r a m 4 r ow 60 ra m 4 - - row 4 r a m4 - - co m 6 1 r ow 61 ra m 6 1 r ow 5 r a m 5 r ow 61 ra m 5 - - row 5 r a m5 - - co m 6 2 r ow 62 ra m 6 2 r ow 6 r a m 6 r ow 62 ra m 6 - - row 6 r a m6 - - co m 6 3 r ow 63 ra m 6 3 r ow 7 r a m 7 r ow 63 ra m 7 - - row 7 r a m7 - - 08 0 00 8 56 56 56 00 0 64 0 0 8 o ut put har d w a r e pi n nam e 0 0 0 64 64 0 8 0 d i splay example s refe r to figures : (a) (b) (c) (d) (e) (f) (a) (b) (d) (c) (e) (f) ( ram )
solom on s y s t e c h nov 2007 p 44/68 rev 1.2 SSD1331 t a b l e 14 - examp l e o f set disp la y offset a n d disp lay start l i n e w i th remap displ a y exampl es refe r to figures: (a) (b) (c) (d) (e) (f) (g) s et m u x r at i o( a 8h) c o m s c an d i r ec t i on r em ap ( a 0h a [ 4]) d i s pl ay of f s et ( a 2h) d i s pl ay s t ar t l i ne ( a 1h) c o m 0 r ow 63 r a m 63 r ow 7 r a m 7 r ow 63 r a m 7 r ow 47 r a m 47 - - r ow 47 r a m 7 - - c o m 1 r ow 62 r a m 62 r ow 6 r a m 6 r ow 62 r a m 6 r ow 46 r a m 46 - - r ow 46 r a m 6 - - c o m 2 r ow 61 r a m 61 r ow 5 r a m 5 r ow 61 r a m 5 r ow 45 r a m 45 - - r ow 45 r a m 5 - - c o m 3 r ow 60 r a m 60 r ow 4 r a m 4 r ow 60 r a m 4 r ow 44 r a m 44 - - r ow 44 r a m 4 - - c o m 4 r ow 59 r a m 59 r ow 3 r a m 3 r ow 59 r a m 3 r ow 43 r a m 43 - - r ow 43 r a m 3 - - c o m 5 r ow 58 r a m 58 r ow 2 r a m 2 r ow 58 r a m 2 r ow 42 r a m 42 - - r ow 42 r a m 2 - - c o m 6 r ow 57 r a m 57 r ow 1 r a m 1 r ow 57 r a m 1 r ow 41 r a m 41 - - r ow 41 r a m 1 - - c o m 7 r ow 56 r a m 56 r ow 0 r a m 0 r ow 56 r a m 0 r ow 40 r a m 40 - - r ow 40 r a m 0 - - c o m 8 r o w 5 5 r am 5 5 r o w 6 3 r am 6 3 r o w 5 5 r am 6 3 r o w 3 9 r am 3 9 r o w 4 7 r am 4 7 r o w 3 9 r am 4 7 r o w 4 7 r am 6 3 c o m 9 r o w 5 4 r am 5 4 r o w 6 2 r am 6 2 r o w 5 4 r am 6 2 r o w 3 8 r am 3 8 r o w 4 6 r am 4 6 r o w 3 8 r am 4 6 r o w 4 6 r am 6 2 c o m 10 r ow 53 r a m 53 r ow 61 r a m 61 r ow 53 r a m 61 r ow 37 r a m 37 r ow 45 r a m 45 r ow 37 r a m 45 r ow 45 r a m 61 c o m 11 r ow 52 r a m 52 r ow 60 r a m 60 r ow 52 r a m 60 r ow 36 r a m 36 r ow 44 r a m 44 r ow 36 r a m 44 r ow 44 r a m 60 c o m 12 r ow 51 r a m 51 r ow 59 r a m 59 r ow 51 r a m 59 r ow 35 r a m 35 r ow 43 r a m 43 r ow 35 r a m 43 r ow 43 r a m 59 c o m 13 r ow 50 r a m 50 r ow 58 r a m 58 r ow 50 r a m 58 r ow 34 r a m 34 r ow 42 r a m 42 r ow 34 r a m 42 r ow 42 r a m 58 c o m 14 r ow 49 r a m 49 r ow 57 r a m 57 r ow 49 r a m 57 r ow 33 r a m 33 r ow 41 r a m 41 r ow 33 r a m 41 r ow 41 r a m 57 c o m 15 r ow 48 r a m 48 r ow 56 r a m 56 r ow 48 r a m 56 r ow 32 r a m 32 r ow 40 r a m 40 r ow 32 r a m 40 r ow 40 r a m 56 c o m 16 r ow 47 r a m 47 r ow 55 r a m 55 r ow 47 r a m 55 r ow 31 r a m 31 r ow 39 r a m 39 r ow 31 r a m 39 r ow 39 r a m 55 c o m 17 r ow 46 r a m 46 r ow 54 r a m 54 r ow 46 r a m 54 r ow 30 r a m 30 r ow 38 r a m 38 r ow 30 r a m 38 r ow 38 r a m 54 c o m 18 r ow 45 r a m 45 r ow 53 r a m 53 r ow 45 r a m 53 r ow 29 r a m 29 r ow 37 r a m 37 r ow 29 r a m 37 r ow 37 r a m 53 c o m 19 r ow 44 r a m 44 r ow 52 r a m 52 r ow 44 r a m 52 r ow 28 r a m 28 r ow 36 r a m 36 r ow 28 r a m 36 r ow 36 r a m 52 c o m 20 r ow 43 r a m 43 r ow 51 r a m 51 r ow 43 r a m 51 r ow 27 r a m 27 r ow 35 r a m 35 r ow 27 r a m 35 r ow 35 r a m 51 c o m 21 r ow 42 r a m 42 r ow 50 r a m 50 r ow 42 r a m 50 r ow 26 r a m 26 r ow 34 r a m 34 r ow 26 r a m 34 r ow 34 r a m 50 c o m 22 r ow 41 r a m 41 r ow 49 r a m 49 r ow 41 r a m 49 r ow 25 r a m 25 r ow 33 r a m 33 r ow 25 r a m 33 r ow 33 r a m 49 c o m 23 r ow 40 r a m 40 r ow 48 r a m 48 r ow 40 r a m 48 r ow 24 r a m 24 r ow 32 r a m 32 r ow 24 r a m 32 r ow 32 r a m 48 c o m 24 r ow 39 r a m 39 r ow 47 r a m 47 r ow 39 r a m 47 r ow 23 r a m 23 r ow 31 r a m 31 r ow 23 r a m 31 r ow 31 r a m 47 c o m 25 r ow 38 r a m 38 r ow 46 r a m 46 r ow 38 r a m 46 r ow 22 r a m 22 r ow 30 r a m 30 r ow 22 r a m 30 r ow 30 r a m 46 c o m 26 r ow 37 r a m 37 r ow 45 r a m 45 r ow 37 r a m 45 r ow 21 r a m 21 r ow 29 r a m 29 r ow 21 r a m 29 r ow 29 r a m 45 c o m 27 r ow 36 r a m 36 r ow 44 r a m 44 r ow 36 r a m 44 r ow 20 r a m 20 r ow 28 r a m 28 r ow 20 r a m 28 r ow 28 r a m 44 c o m 28 r ow 35 r a m 35 r ow 43 r a m 43 r ow 35 r a m 43 r ow 19 r a m 19 r ow 27 r a m 27 r ow 19 r a m 27 r ow 27 r a m 43 c o m 29 r ow 34 r a m 34 r ow 42 r a m 42 r ow 34 r a m 42 r ow 18 r a m 18 r ow 26 r a m 26 r ow 18 r a m 26 r ow 26 r a m 42 c o m 30 r ow 33 r a m 33 r ow 41 r a m 41 r ow 33 r a m 41 r ow 17 r a m 17 r ow 25 r a m 25 r ow 17 r a m 25 r ow 25 r a m 41 c o m 31 r ow 32 r a m 32 r ow 40 r a m 40 r ow 32 r a m 40 r ow 16 r a m 16 r ow 24 r a m 24 r ow 16 r a m 24 r ow 24 r a m 40 c o m 32 r ow 31 r a m 31 r ow 39 r a m 39 r ow 31 r a m 39 r ow 15 r a m 15 r ow 23 r a m 23 r ow 15 r a m 23 r ow 23 r a m 39 c o m 33 r ow 30 r a m 30 r ow 38 r a m 38 r ow 30 r a m 38 r ow 14 r a m 14 r ow 22 r a m 22 r ow 14 r a m 22 r ow 22 r a m 38 c o m 34 r ow 29 r a m 29 r ow 37 r a m 37 r ow 29 r a m 37 r ow 13 r a m 13 r ow 21 r a m 21 r ow 13 r a m 21 r ow 21 r a m 37 c o m 35 r ow 28 r a m 28 r ow 36 r a m 36 r ow 28 r a m 36 r ow 12 r a m 12 r ow 20 r a m 20 r ow 12 r a m 20 r ow 20 r a m 36 c o m 36 r ow 27 r a m 27 r ow 35 r a m 35 r ow 27 r a m 35 r ow 11 r a m 11 r ow 19 r a m 19 r ow 11 r a m 19 r ow 19 r a m 35 c o m 37 r ow 26 r a m 26 r ow 34 r a m 34 r ow 26 r a m 34 r ow 10 r a m 10 r ow 18 r a m 18 r ow 10 r a m 18 r ow 18 r a m 34 c o m 38 r ow 25 r a m 25 r ow 33 r a m 33 r ow 25 r a m 33 r ow 9 r a m 9 r ow 17 r a m 17 r ow 9 r a m 17 r ow 17 r a m 33 c o m 39 r ow 24 r a m 24 r ow 32 r a m 32 r ow 24 r a m 32 r ow 8 r a m 8 r ow 16 r a m 16 r ow 8 r a m 16 r ow 16 r a m 32 c o m 40 r ow 23 r a m 23 r ow 31 r a m 31 r ow 23 r a m 31 r ow 7 r a m 7 r ow 15 r a m 15 r ow 7 r a m 15 r ow 15 r a m 31 c o m 41 r ow 22 r a m 22 r ow 30 r a m 30 r ow 22 r a m 30 r ow 6 r a m 6 r ow 14 r a m 14 r ow 6 r a m 14 r ow 14 r a m 30 c o m 42 r ow 21 r a m 21 r ow 29 r a m 29 r ow 21 r a m 29 r ow 5 r a m 5 r ow 13 r a m 13 r ow 5 r a m 13 r ow 13 r a m 29 c o m 43 r ow 20 r a m 20 r ow 28 r a m 28 r ow 20 r a m 28 r ow 4 r a m 4 r ow 12 r a m 12 r ow 4 r a m 12 r ow 12 r a m 28 c o m 44 r ow 19 r a m 19 r ow 27 r a m 27 r ow 19 r a m 27 r ow 3 r a m 3 r ow 11 r a m 11 r ow 3 r a m 11 r ow 11 r a m 27 c o m 45 r ow 18 r a m 18 r ow 26 r a m 26 r ow 18 r a m 26 r ow 2 r a m 2 r ow 10 r a m 10 r ow 2 r a m 10 r ow 10 r a m 26 c o m 46 r ow 17 r a m 17 r ow 25 r a m 25 r ow 17 r a m 25 r ow 1 r a m 1 r ow 9 r a m 9 r ow 1 r a m 9 r ow 9 r a m 25 c o m 47 r ow 16 r a m 16 r ow 24 r a m 24 r ow 16 r a m 24 r ow 0 r a m 0 r ow 8 r a m 8 r ow 0 r a m 8 r ow 8 r a m 24 c o m 48 r ow 15 r a m 15 r ow 23 r a m 23 r ow 15 r a m 23 - - r ow 7 r a m 7 - - r ow 7 r a m 23 c o m 49 r ow 14 r a m 14 r ow 22 r a m 22 r ow 14 r a m 22 - - r ow 6 r a m 6 - - r ow 6 r a m 22 c o m 50 r ow 13 r a m 13 r ow 21 r a m 21 r ow 13 r a m 21 - - r ow 5 r a m 5 - - r ow 5 r a m 21 c o m 51 r ow 12 r a m 12 r ow 20 r a m 20 r ow 12 r a m 20 - - r ow 4 r a m 4 - - r ow 4 r a m 20 c o m 52 r ow 11 r a m 11 r ow 19 r a m 19 r ow 11 r a m 19 - - r ow 3 r a m 3 - - r ow 3 r a m 19 c o m 53 r ow 10 r a m 10 r ow 18 r a m 18 r ow 10 r a m 18 - - r ow 2 r a m 2 - - r ow 2 r a m 18 c o m 54 r ow 9 r a m 9 r ow 17 r a m 17 r ow 9 r a m 17 - - r ow 1 r a m 1 - - r ow 1 r a m 17 c o m 55 r ow 8 r a m 8 r ow 16 r a m 16 r ow 8 r a m 16 - - r ow 0 r a m 0 - - r ow 0 r a m 16 c o m 5 6 r o w 7 r a m 7 r o w 1 5 r a m 1 5 r o w 7 r a m 1 5 ------ -- c o m 5 7 r o w 6 r a m 6 r o w 1 4 r a m 1 4 r o w 6 r a m 1 4 ------ -- c o m 5 8 r o w 5 r a m 5 r o w 1 3 r a m 1 3 r o w 5 r a m 1 3 ------ -- c o m 5 9 r o w 4 r a m 4 r o w 1 2 r a m 1 2 r o w 4 r a m 1 2 ------ -- c o m 6 0 r o w 3 r a m 3 r o w 1 1 r a m 1 1 r o w 3 r a m 1 1 ------ -- c o m 6 1 r o w 2 r a m 2 r o w 1 0 r a m 1 0 r o w 2 r a m 1 0 ------ -- c o m 6 2 r o w 1 r a m 1 r o w 9 r a m 9 r o w 1 r a m 9 ------ -- com63row0ram0row8ram8row0ram8-------- 48 48 1 111 h a rd w a re pi n nam e o utput 64 64 64 48 48 11 0 8008 08 1 08 1 6 0 080 (a ) (b ) (d) (c) (e ) (f) ( g ) ( ram )
SSD1331 rev 1.2 p 45/68 nov 2007 s o l o mo n s y st ec h 9.1.9 set displa y mode (a4h ~ a7h) the s e are sin g le byte com m and a nd the y are used to set no rmal di splay, entire display on, entire di spla y off and inve rse di splay. ? no rmal di spl ay (a4h) re set the ab ove effect an d turn the dat a to on at the co rre sp ondi ng gray level. ? set entire display on (a5h) force s the en tire display to be at ?gs63 ? rega rd le ss of the content s of the display data ram. ? set entire dis p lay off (a6 h ) force s the en tire display to be at gray le vel ?gs0? re g a rdl e ss of the content s of the display da ta ram. ? inverse di spl ay (a7h) the gray level of display da ta are swa p p ed su ch that ? gs0? < - > ?g s63?, ?gs1 ? <- > ?gs 62?, ?. 9.1.10 set multiple x ratio (a8h ) this comm an d swit che s de fault 1:64 mul t iplex mode to any multipl e x mode from 16 to 64. for example, whe n multiple x ratio is set to 16, only 16 comm on pin s are en able d . the startin g and the en din g of the enabl ed com m on pin s are depe nde d on the setting of ?displ ay offset? regi ster p r ogramme d by comma nd a2h. 9.1.11 dim mode s e tting (abh) this comm an d contai ns m u ltiple bits to c onfig ure the dim mode di splay paramet ers. cont ra st setting of colo r a, b, c and pre c ha rg e volt ag e can b e set different to no rmal mo de (a fh). 9.1.12 set master configuration (adh) this comm an d sele cts the external v cc power sup p ly. external v cc powe r sh oul d be co nne ct ed to the v cc pin. a[0] bit mus t be s e t to 0b after reset. this comm an d will be a c tivated after issuing set di sp lay on co mm and (af h) 9.1.13 set displa y on/off (ac h / aeh / afh) the s e si ngle byte comma n d s a r e u s ed t o turn the ol ed pan el display on o r o ff. whe n the display is on, th e sele cted circuits by set maste r co nfiguration com m and will be turn ed o n . whe n the display is off, those ci rcuits will be tur ned off and the segm ent an d comm on o utput are in h i gh imped an ce st ate. the s e comm and s set the displ a y to one of the three states: o ach : dim m ode di spl ay on o aeh : display off (sl eep mode ) o afh : normal brightne ss display o n whe r e the di m mode settings a r e controlled by co m m and abh. figure 2 7 ? tra n s i tion be t w e e n diffe re nt mode s no rmal mo de dim mode slee p mode afh aeh ach afh ach aeh
solom on s y s t e c h nov 2007 p 46/68 rev 1.2 SSD1331 9.1.14 po w e r save mode (b0h) this comm an d is used in e nablin g or di sabling the p o w e r save mo de. 9.1.15 phase 1 and 2 period adjustment (b1h) this comm an d sets the le n g th of phase 1 and 2 of se gment waveform of the dri v er. ? phase 1 (a[3:0]): set the perio d from 1 to 15 in the unit of dclks . a larger c a pac i tanc e of the oled pixel may req u ire lo nge r pe riod to di scha rge the p r evio us data cha r g e com p letely. ? phase 2 (a[7:4]): set the perio d from 1 to 15 in the un it of dclks. a longer p e ri od is ne ede d to cha r g e up a l a rg er capa cit ance of the oled pixel to the targ et voltage v p for col o r a, b and c. 9.1.16 set display clo ck divide ratio/ oscillator frequ e nc y (b3h) this c o mmand c o ns is ts of two func tions : ? d i splay c l ock d i vide r a tio ( a [3:0]) set the divide ratio to gene rate dclk (display cl ock) from clk. the divide ratio is from 1 to 16, with re set value = 1. please ref er to se ction 7.3.1 for the details relatio n shi p of dcl k and clk. ? oscillato r fre quen cy (a[7:4]) program the oscillator frequen cy fosc that is the source of clk if cls pin i s pulled high. the 4-bit value re sult s in 16 differe nt frequ en cy set t ings availa bl e as sho w n b e low. the d e f ault setting is 1101 b figure 28 - ty pical oscillato r freque ncy adjustment by b3 command (v dd =2.7v) 9.1.17 set gra y sc ale table (b8h) this comm an d is used to set the gray scale table for t he di splay. except gray scale entry 0, which i s ze ro a s it has no p r e-cha r g e and current drive, each odd e n try gray scale l e vel is progra mmed in the l ength of cu rrent drive sta ge p u lse width wit h unit of dcl k. the longe r t he length of the pulse wid t h, the brighte r is the ole d pixel when it?s turned on. pleas e refer to s e c t ion 7.6 for more d e tailed expla n a t ion of relatio n of display d a ta ram, gray scale table an d the pixel brig htness. follo wing the comma nd b 8h, the use r h a s to set the pul se width fo r gs1, gs3, gs5, ?, gs59, gs61, and gs63 on e by one in sequ e n ce a nd com p lies the follo wing con d itio ns. gs1 > 0; gs3 > gs1 + 1; gs5 > gs3 + 1; ?? afterwa r d s , the drive r auto m atically de ri ves the pul se wi dth of even entry of gra y scale tabl e gs2, gs4, ?, gs62 with th e formula li ke below. gsn = (gs n-1 + gsn + 1) / 2 for exam ple, if gs1 = 3 dclk s and gs 3 = 7 dclk s, gs2 = (3 +7 )/2 = 5 dclk s the setting of gray scale ta ble entry can perfo rm gam ma co rrectio n on oled p a nel display. no rmally, it is desi r e d that the bri ghtne ss respon se of the pan el is lin early propo rti onal to the im age data valu e in displ a y note (1 ) t here is 10% tolera nce in the freque nc y values
SSD1331 rev 1.2 p 47/68 nov 2007 s o l o mo n s y st ec h data ram. howeve r, the oled p anel i s so meh o w resp ond ed in non -line a r wa y. appropriat e gray scal e table setting like example b e lo w can com pen sate this effect . f i g u r e 29 - examp l e o f g a mma co rr ectio n b y g r a y s cale tab l e settin g 9.1.18 enable line ar gra y sc ale table (b9 h ) this comm an d relo ad s the pre s et line ar gray scal e t able as gs 1 = 1, gs2 = 3, gs3 = 5, ?., gs62 = 1 23, gs63 = 1 25 dclks. 9.1.19 set pre-cha rge voltage (bbh) this comma nd sets the pre - cha r ge voltage le vel of segme n t pins. the le vel of v p is p r og r a mme d w i th referenc e to v cc . figure 30 sho w s the details of setting pre - charg e voltage level by comma nd bbh a[5:1]. f i g u r e 30 ? t y p i cal pre-ch ar g e v o ltag e le v e l settin g b y co mman d bbh . v p ratio vs bbh a[5:1] setting 0 0. 1 0. 2 0. 3 0. 4 0. 5 0. 6 00 00 0 00 00 1 00 01 0 00 01 1 00 10 0 00 10 1 00 11 0 00 11 1 01 00 0 01 00 1 01 01 0 01 01 1 01 10 0 01 10 1 01 11 0 01 11 1 10 00 0 10 00 1 10 01 0 10 01 1 10 10 0 10 10 1 10 11 0 10 11 1 11 00 0 11 00 1 11 01 0 11 01 1 11 10 0 11 10 1 11 11 0 11 11 1 bb h a[5:1] setting v p rat i o not e (! ) v p ratio = 0.1 refers to v p voltage = 0.1 x v cc. 9.1.20 set v com h voltage (beh) this comm an d sets the hi g h voltage level of commo n pins. the lev e l of v co m h is programmed with reference to v cc . 9.1.21 nop (bch, bdh, e3h) the s e are co mmand fo r n o ope ration. 9.1.22 set command lock (fdh) this comm an d is used to lock the ole d drive r ic fr om acce pting any comma n d ex cept itself . after enterin g fdh 16h (a[2]=1b), the ol ed driver ic will not re spond to any newly entered command (ex c ept fdh 12h a[2]=0b) a nd there will be no memo ry a c cess. thi s is call ?l ock? state. that means the o l e d drive r ic ig nore all the comm and s (ex c ept fdh 1 2h a[2] =0b ) du ring t he ?l ock? state. entering f d h 12h (a[2]=0 b ) ca n unlo c k the ole d driv er ic. that m ean s the driv er ic re su me from the ?l ock? state. and the driver ic wil l then re spo n d to the com m and a nd me mory acce ss. puls e width gray scal e panel response brightne ss brightne ss pulse width gray scal e gray scal e table setting result in linear re spo n s e
solom on s y s t e c h nov 2007 p 48/68 rev 1.2 SSD1331 9.2 gra phic accel era tion c o mman d set desc ripti o n 9.2.1 dra w line ( 21h) this comm an d dra w s a lin e by the given start, end colu mn a nd ro w co ordinate s and the col or of the line. figure 3 1 - ex a m ple of dra w l i ne comma nd for exam ple, the line abov e can b e dra w n by the followin g co mm and sequ en ce. 1. enter into dra w line mo de by comma nd 21h 2. send column start ad dre s s of line, colum n1, for examp l e = 1h 3. send ro w sta r t address of li ne, ro w 1, for example = 1 0h 4. send column end ad dress of line, colum n 2, for example = 28 h 5. send ro w en d add re ss of l i ne, ro w 2, for example = 4 h 6. send color c, b and a of line, for examp l e = 35d, 0d, 0d for blu e co lor 9.2.2 dra w rectangle (22h) given the sta r ting point (row 1, colum n 1) and the endi ng p o int (ro w 2, colu mn 2), spe c if y the outline and fill area colors, a rectangle that will be dr awn with the col or specifie d. rem a rks: if fi ll color option is disabl ed, the encl o sed area will not be filled. f i g u re 32 - examp l e o f draw rectan g l e co mman d the follo wing example illu strates the rect angle d r a w in g comm and seque nce. 1. enter the ?d ra w re ctan gle m ode ? by execute the com m and 2 2h 2. set the starting col u mn co ordi nate s , co lumn 1. e.g., 03h. 3. set the starting ro w coordi nates, row 1. e.g., 02h. 4. set the finishi ng col u mn co ordi nate s , co lumn 2. e.g., 12h 5. set the finishi ng ro w coordi nates, row 2. e.g., 15h 6. set the outline colo r c, b and a. e.g., (28d, 0d, 0d) fo r blue colo r 7. set the filled colo r c, b an d a. e.g., (0d, 0d, 40d) for red col o r ro w 1, colu mn 1 row 2, column 2 line colo r ro w 1, colu mn 1 row 2, column 2 outline colo r filled color
SSD1331 rev 1.2 p 49/68 nov 2007 s o l o mo n s y st ec h 9.2.3 cop y ( 23h) copy the rect angul ar regio n defined by the sta r ting po int (ro w 1, column 1 ) and the endin g po int (ro w 2, colu mn 2) to locatio n (ro w 3, column 3 ) . if the new coordinate s are small e r tha n the endin g points, the ne w image will overla p the origi nal one. the following example illust rates the copy procedure. 1. enter the ?co p y mode? by execute the comman d 23h 2. set the starting col u mn co ordi nate s , co lumn 1. e.g., 00h. 3. set the starting ro w coordi nates, row 1. e.g., 00h. 4. set the finishi ng col u mn co ordi nate s , co lumn 2. e.g., 05h 5. set the finishi ng ro w coordi nates, row 2. e.g., 05h 6. set the new column coo r di nates, colum n 3. e.g., 03h 7. set the new row coo r din a tes, ro w 3. e.g., 03h figure 3 3 - ex a m ple of cop y comma nd 9.2.4 dim window ( 24h) this comm an d will dim th e win do w are a sp ecify by startin g point (ro w 1, col umn 1 ) and t he en ding p o i nt (row 2, colu mn 2). after the executio n of this com m and, the se lected wi ndo w are a will beco m e darke r as follow. t a b l e 15 - res u lt o f ch an g e o f brig h t n ess b y dim w i n d o w c o mman d origi nal gray scale ne w gray sca l e after dim windo w co mm and gs0 ~ gs15 no change gs16 ~ gs19 gs4 gs20 ~ gs23 gs5 : : gs60 ~ gs63 gs15 additional ex ecutio n of this co mman d o v er the sa m e wind ow a r e a will not ch ang e the data co ntent. row 3 + row 2, column 3 + column 2 ro w 1, colu mn 1 ro w 3, colu mn 3 origi nal image new copied image
solom on s y s t e c h nov 2007 p 50/68 rev 1.2 SSD1331 9.2.5 clear window ( 25h) this comma n d sets the wi ndo w are a sp ecify by starting point (ro w 1, colum n 1) and the en ding poi nt (row 2, colu mn 2) to clear the win dow di splay. the gra phi c displ a y data ram conte n t of the specifi ed wind ow a r ea will be set to zero. this comm an d ca n be co mbine d with copy comm a nd to ma ke a s a ?m ove? result. the fo llowin g exam ple illustrates the copy plu s cle a r procedu re and results in moving the wind ow o b je ct. 1. enter the ?co p y mode? by execute the comman d 23h 2. set the starting col u mn co ordi nate s , co lumn 1. e.g., 00h. 3. set the starting ro w coordi nates, row 1. e.g., 00h. 4. set the finishi ng col u mn co ordi nate s , co lumn 2. e.g., 05h 5. set the finishi ng ro w coordi nates, row 2. e.g., 05h 6. set the new column coo r di nates, colum n 3. e.g., 06h 7. set the new row coo r din a tes, ro w 3. e.g., 06h 8. enter the ?cle ar mod e ? by execute the comman d 25h 9. set the starting col u mn co ordi nate s , co lumn 1. e.g., 00h. 10. set the starting ro w coordi nates, row 1. e.g., 00h. 11. set the finishi ng col u mn co ordi nate s , co lumn 2. e.g., 05h 12. set the finishi ng ro w coordi nates, row 2. e.g., 05h f i g u r e 34 - examp l e o f co py + clea r = mo v e co m m an d 9.2.6 fill enable/ d isable (26h) this comm an d has two fun c tion s. ? enable/ disab le fill (a[0]) 0 = di sabl e filling of color i nto rect angl e in draw rectangle command. (reset) 1 = enabl e filling of colo r in to recta ngle i n dra w re ctan gle co mman d . ? enable/ disab l e reverse co py (a[4]) 0 = dis able revers e copy (reset) 1 = du rin g co py comma nd, the new ima ge col ors are swapp ed such that ?gs0? <-> ?gs 63?, ?gs1? <- > ?gs6 2?, ?. clear c o mmand
SSD1331 rev 1.2 p 51/68 nov 2007 s o l o mo n s y st ec h 9.2.7 continuous horizontal & vertical scrolling setup (27h) this comm an d setup the p a ram e ters re quired for ho rizontal a nd vertical scrolli n g . t he parame t ers shoul d not be chan ged after scrolli ng is acti vated figure 35 - examples of continu ous hori z ontal and vertical scrollin g command setup sta r t r o w ad dre ss no of scrolling rows display before scrolling start display snap shot after scrolling start samp l e cod e 2 7h / / co nt in uo us ho r i zo nt al scrol l 01 h // h o r iz o nt al sc r o ll b y 1 c o lu m n 28 h // d e fi ne r o w 4 0 as s t a r t r o w ad dr es s 1 8h / / scro ll in g 24 r o ws 0 0h / / no vert ical scrol l 00 h // s e t ti me i n te r v al b e tw ee n ea ch s c r ol l s t e p as 6 fr a m es 2f h // a c tiv a t e sc r o ll in g exam ple 2 : f u ll sc ree n ve r tical scrolling with 1 row up in every 6 frames. exa mple 3 : full sc ree n di ag on al scr o ll in g ( h o r izo n t a l le f t si de scr o ll in g wit h 1 col u m n shi f t plus vertical scrolling with 1 row up) in every 10 frames. st ar t r o w ad dr es s samp le cod e 2 7h / / co nt in uo us di ag on al scrol l 0 1h / / h o ri zon t al s c rol l by 1 col u m n 0 0h / / defi ne r o w 0 as st a r t row ad dress 4 0h / / scrol l in g 64 ro ws 01 h // s e t v e r t ic a l s c r ol li ng o ffs et as 1 r o w 01 h // s e t ti me i n te r v a l b e t w ee n ea c h s c r o ll st ep as 1 0 fr a m es 2f h // a c tiv a te sc r o ll in g no o f s c r o llin g rows samp le cod e 2 7h / / co nt in uo us ve rti c a l scro l l 0 0h / / no ho rizo nt al scro l l 00 h // s t a r t r o w addr e s s fo r ver t i c al s c r o ll ing 4 0h / / nu mbe r o f scrol l i n g ro w s f o r vert ical scrol l i n g 01 h // s e t v e r t ic al s c r ol li ng o ffs et as 1 r o w 00 h // s e t ti me i n te r v al b e tw ee n ea c h s c r ol l s t e p as 6 fr am es 2f h // a c tiv a te sc r o ll in g exam pl e 1 : pa r t i a l scr ee n horizontal left side scrolling with 1 column shift in every 6 frames display snap shot after scrolling start display snap shot after scrolling start display before scrolling start display before scrolling start 9.2.8 deactivate scrolling (2eh) this command deactivates the scrolling action. after sendi ng 2e h co mmand to de a c tivate the scro llin g action , the ram data ne ed s to be re w ritte n. 9.2.9 activate scrolling (2fh) this comm an d activates th e scrolli ng fu nction a c co rd ing to the setting don e by contin uou s hori zontal & vertical s c roll ing setup co mmand 2 7h.
solom on s y s t e c h nov 2007 p 52/68 rev 1.2 SSD1331 10 maximum ratings t a b l e 16 - maximu m ratin g s (voltage refe ren c e to v ss ) symbol para mete r value unit v dd -0.3 to +4 v v ddio -0.3 to v dd +0.5 v v cc supp l y v o ltag e 0 to 19.0 v v seg seg output voltage 0 to v cc v v com com output voltag e 0 to 0.9* v cc v v in input voltag e v ss -0.3 to v dd +0.3 v t a operatin g t e mperatur e -40 to + 85 oc t st g storage t e mperature r ang e -65 to + 150 oc *maxi m um rati n g s are those val ues be y ond whi c h damage to the d e vi ce may occur. functi onal oper ati on shoul d be r e stri cted to th e l i m i t s i n the el ect r i c al characteri sti cs tabl es or pi n descri p ti on. *thi s devi c e may be l i ght sensi t i v e . cauti on shoul d be taken to av oi d exposur e of thi s devi c e to an y l i ght source duri ng normal oper ati o n . thi s devi c e i s no t radi ati on protec ted.
SSD1331 rev 1.2 p 53/68 nov 2007 s o l o mo n s y st ec h 11 dc characte r ist i cs t a b l e 17 - dc ch aracteristic s condition s (unless sp eci fied): voltage refe renced to v ss v dd = 2.7, v dd i o = 1.8v, v cc = 11.0v, i re f = 10ua, at t a = 25 c. sy mbol parameter test conditi on min t y p max unit v cc ope r ating vol t age - 8 11 18 v v dd logi c supply voltage - 2.4 2.7 3.5 v v ddio powe r suppl y for i/o pins - 1.6 1.8 v dd v v oh high l ogi c o utput level i out = 100ua, 3.3mhz 0.9 x v ddi o - v ddio v v ol low l ogi c ou tput level i out = 100ua, 3.3mhz 0 - 0.1 x v ddi o v v ih high l ogi c input level - 0.8 x v ddi o - v ddio v v il low l ogi c input level - 0 - 0.2 x v ddi o v i dd_sl eep sleep mod e v dd curre nt display off, no pa nel atta che d - 0 10 ua i ddio sleep sleep mod e v ddio current display off, no pa nel atta che d - 0 10 ua i cc_sl eep sleep mod e v cc curre nt display off, no pa nel atta che d - 0 10 ua i cc v cc supply current display on, all 1?s pattern, contras t = ffh, no panel attac h ed - 790 1200 ua i dd v dd supply current display on, all 1?s pattern, contras t = ffh, no panel attac h ed - 170 500 ua cont ra st = ff h 126 140 154 ua cont ra st = 7f h - 68 - ua i seg segment out put cu rre nt: v dd = v ddi o = 2.7v, v cc = 8v, display on, all 1?s pattern. (segm ent pin unde r test is con ne c ted wit h a 20k ? re sist iv e loa d t o v ss ) cont ra st = 3f h - 33 - ua dev segment out put cu rre nt uniformity: dev = (i seg ? i mi d ) / i mi d i mi d = (i ma x + i mi n ) / 2 i s eg [0:287] = segment cu rre nt at con t rast settings v cc =12v cont ra st = ff h -3 - +3 % adj. dev adjacent pin output cu rre nt uniformity: adj dev = (i[n] - i[n+ 1 ]) / (i[n]+ i[n+ 1 ]) cont ra st = ff h -2 - +2 % r com _ on com pi n out put re sista n ce com[0:6 3 ], i = 20ma - 25 30
solom on s y s t e c h nov 2007 p 54/68 rev 1.2 SSD1331 12 ac characte r ist i cs t a b l e 18 - a c ch aract eristic s condition s (unles s othe r w i s e spe c ified): voltage refe renced to v ss v dd = v ddi o = 2.4v to 3.5v v cc = 8.0v to 18.0v t a = 25 c sym bol par a meter test co nditio n min t yp ma x u nit f osc oscillation f r eque ncy of d i splay timing gene rato r v dd = 2.7v, v cc = 11.0v 800 890 980 khz f frm fram e fre qu ency display on, internal oscillato r enabled - f osc x 1 / ( d x k x n ) - hz re set low p u l s e wi dth - 3 - - us res# res e t c o mpletion time - - - 2 us not e (1) fosc st and s for the freq uen cy value of the internal oscill ator a n d the value is measure d when comma n d b3h a[7:4]=1 101b [defa u lt value] (2) d stand s for divide ratio (3) k stands for total number of displ a y cl ocks per row. (reset=136, i.e. phase1 dclk + phase2 dclk + pha se3 dcl k =4+7+125 ) (4) n stand s for numb er of mux sel ecte d by comma n d a8h
SSD1331 rev 1.2 p 55/68 nov 2007 s o l o mo n s y st ec h t a b l e 19 - 680 0-serie s mpu parallel in terface t i min g ch aract eristics ( v dd - v ss = 2.4v to 3.5v, v ddio = 2.4v to v dd , t a = 25c) symbol para mete r min t y p max unit t cy cle clock c y cl e t i me ( w r i te c y c l e ) 130 - - ns pw cs l control p u lse lo w w i dth ( w ri te c y cle) 60 - - ns pw cs h control p u lse high w i dth ( w r i te c y cle) 60 - - ns t cy cle clock c y cl e t i me (read c y cle ) 200 - - ns pw cs l control p u lse lo w w i dth (re a d c y cl e) 100 - - ns pw cs h control p u lse high w i dth (re ad c y c l e) 100 - - ns t as address setu p t i me 0 - - ns t ah address h o ld t i me 10 - - ns t ds w data setup t i me 40 - - ns t dh w data hol d t i me 10 - - ns t ac c data access t i me - - 140 ns t oh output hold ti me - - 70 ns t r ri s e ti me - - 15 ns t f fal l ti me - - 15 ns f i g u r e 36 - 6800-s e ries p a r a llel interface c h aract eristics t cycle d[15:0] (w rite) d[15:0] (read) e pw csh t r t f t dh w t oh t acc t dhr valid data t ds w valid data pw csl t ah t as d/c# r/w# cs#
solom on s y s t e c h nov 2007 p 56/68 rev 1.2 SSD1331 t a b l e 20 - 808 0-serie s mpu parallel in terface t i min g ch aract eristics ( v dd - v ss = 2.4v to 3.5v, v ddio = 2.4v to v dd , t a = 25c) symbol para mete r min t y p max unit t cy cl e cl ock cy cl e ti m e 130 - - ns t as address setup ti me 10 - - ns t ah address hol d ti me 0 - - ns t ds w wri t e data setup ti me 40 - - ns t dh w wri t e data hol d ti me 10 - - ns t dhr read data hol d ti me 20 - - ns t oh o utput di sabl e ti me - - 70 ns t acc access ti me - - 140 ns t pw l r read lo w ti me 150 - - ns t pw l w wri t e lo w ti me 60 - - ns t pw h r read hi gh ti me 60 - - ns t pw hw wri t e hi gh ti me 60 - - ns t r ri s e ti me - - 15 ns t f fal l ti me - - 15 ns t cs chi p sel e ct setup ti me 0 - - ns t csh chi p sel e ct hol d ti me to read si gna l 0 - - ns t csf chi p sel e ct hol d ti me 20 - - ns wr # d[7:0] t as d/c# cs# t cs t ah t pwlw t c ycle t dsw t dhw t pwhw t csf rd # d[7:0] t as d/c# cs# t cs t ah t pwlr t cycle t pwhr t csh t acc t dhr t oh t f t r t f t r write c y c l e ( f orm 1) r e ad cycle (for m 1) figure 37 - 8 080 -serie s p arallel interface ch arac te ristics (f orm 1) wr # d[7:0] d/c# cs# t cycle t pw lw t pwh w t f t r t cs t as t ah t cs f t ds w t dh w rd# d[7:0] d/c# cs# t cycl e t pw lr t pwh r t f t r t cs t as t ah t acc t dhr t oh t csh wri t e cy c l e (form 2 ) read cy c l e (form 2 ) f i g u r e 38 - 8080-s e ries p a r a llel interface c h aract eristics ( form 2)
SSD1331 rev 1.2 p 57/68 nov 2007 s o l o mo n s y st ec h t a b l e 21 - serial in terface t i min g ch aracteristics ( v dd - v ss = 2.4v to 3.5v, v ddio = 2.4v to v dd , t a = 25c) symbol para mete r min t y p max unit t cy cl e cl ock cy cl e ti m e 150 - - ns t as address setup ti me 40 - - ns t ah address hol d ti me 40 - - ns t css chi p sel ect setup ti me 75 - - ns t csh c h ip se le ct h o ld t i m e 6 0 - - ns t ds w wri t e data setup ti me 40 - - ns t dh w wri t e data hol d ti me 40 - - ns t clkl cl ock low ti me 75 - - ns t clkh cl ock hi gh ti me 75 - - ns t r ri s e ti me - - 15 ns t f fal l ti me - - 15 ns t ah t as d/ c# va lid d a ta t dhw t clk l t ds w t clk h t cyc l e t cs s t cs h t f t r sd in ( d 1 ) cs # sc l k( d 0 ) d7 sd in ( d 1 ) cs # sc l k ( d 0 ) d6 d5 d4 d3 d2 d1 d0 f i g u r e 39 - serial in terface c h aract eristics
solom on s y s t e c h nov 2007 p 58/68 rev 1.2 SSD1331 13 application example f i g u r e 40 - a p p licatio n examp l e fo r ssd133 1u1 r 1 color oled panel 96rgb x 64 SSD1331u1 com62 . . com0 sa0 sb0 sc0 . . . . . . . . . . sa95 sb95 sc95 com1 . . com63 nc v cc v co m h nc d7~ d 0 e r/ w # d/c# res# cs# i re f b s2 b s1 v dd vb re f fb v dd b gdr v ss nc d 7 ~ d 0 e r/ w # d/c# r es# cs# v ss [gnd] pi n connected to mcu i n terface: d0~d7, e, r/w# , d/c#, res#, c s # pi n i n ternal l y con nected to v ddio : cls, pi n i n ternal l y con nected to v ss : v ss b , b00 , bs3 pi n i n ternal l y con nected to v dd : a v dd c1: 4.7uf (1 ) c2: 4.7uf (1 ) c3: 4.7uf (1 ) vol t age at i ref = v cc ? 3v r1 = (vol tage at i ref - v ss ) / i re f = 910k for 12v v cc note (1 ) the capaci t or val ue i s recomm ended val ue. sel e ct appropri a te v a l ue agai nst modul e appl i c ati on. r1 c1 c3 c2 the configu r a t ion for 680 0-parallel interf ace m ode, ex ternally v cc is s h own in the following diagram: (v dd = 3.0v, external v cc = 12v, i ref = 10ua)
SSD1331 rev 1.2 p 59/68 nov 2007 s o l o mo n s y st ec h 14 package options 14.1 SSD1331z die tra y information figure 4 1 - di e tray informa tion spec mm (mil) w1 76.00 0.1 0 (2992) w2 68.00 0.1 0 (2677) h 4.20 0.1 0 (165) dx 13.66 0.10 (53 8) tpx 48.78 0.10 (19 20) dy 7.550.10 (297) tpy 61.00 0.10 (24 02) px 16.26 0.0 5 (640) py 3.05 0.05 (120) x 13.25 0.0 1 (522) y 1.73 0.01 (68) z 0.62 0.05 (24) n 84 (po c ket numbe r)
solom on s y s t e c h nov 2007 p 60/68 rev 1.2 SSD1331 14.2 SSD1331u1 r 1 cof package di mensions f i g u re 42 - ssd133 1u 1r1 o u tlin e d ra w in g
SSD1331 rev 1.2 p 61/68 nov 2007 s o l o mo n s y st ec h
solom on s y s t e c h nov 2007 p 62/68 rev 1.2 SSD1331 14.3 SSD1331u1 r 1 cof package pi n assignment f i g u re 43 - ssd133 1u 1r1 p i n assig n men t d ra w in g
SSD1331 rev 1.2 p 63/68 nov 2007 s o l o mo n s y st ec h t a b l e 22 - ssd133 1u 1r1 p i n assig n m en t p i n no . p i n na m e p i n no . p in nam e p i n no. p i n na m e p i n n o. p i n n a m e p i n no. p i n nam e p i n n o. p i n n a m e 1 n c 8 1 sa9 3 1 6 1 sb6 6 2 41 s c 3 9 32 1 sa1 3 4 01 nc 2 v cc 82 sc 92 16 2 sa6 6 2 42 sb39 3 2 2 sc1 2 3 v c o m h 83 sb9 2 1 6 3 sc6 5 2 4 3 sa39 3 2 3 sb1 2 4 n c 8 4 sa9 2 1 6 4 sb6 5 2 44 s c 3 8 32 4 sa1 2 5 d 7 8 5 s c 9 1 1 6 5 sa6 5 2 45 sb38 3 2 5 sc1 1 6 d 6 8 6 sb9 1 1 6 6 sc6 4 2 4 6 sa38 3 2 6 sb1 1 7 d 5 8 7 sa9 1 1 6 7 sb6 4 2 47 s c 3 7 32 7 sa1 1 8 d 4 8 8 s c 9 0 1 6 8 sa6 4 2 48 sb37 3 2 8 sc1 0 9 d 3 8 9 sb9 0 1 6 9 sc6 3 2 4 9 sa37 3 2 9 sb1 0 10 d2 90 sa9 0 1 7 0 sb6 3 2 50 s c 3 6 33 0 sa1 0 11 d1 91 sc89 17 1 sa6 3 2 51 sb36 3 3 1 sc9 12 d0 92 sb8 9 1 7 2 sc6 2 2 5 2 sa36 3 3 2 sb9 13 e 9 3 sa8 9 1 7 3 sb6 2 2 53 s c 3 5 33 3 sa9 14 r/ w # 94 sc88 17 4 sa6 2 2 54 sb35 3 3 4 sc8 15 d/ c# 95 sb8 8 1 7 5 sc6 1 2 5 5 sa35 3 3 5 sb8 16 res# 96 sa8 8 1 7 6 sb6 1 2 56 s c 3 4 33 6 sa8 17 cs# 9 7 s c 8 7 1 7 7 sa6 1 2 57 sb34 3 3 7 sc7 18 i r ef 98 sb8 7 1 7 8 sc6 0 2 5 8 sa34 3 3 8 sb7 19 bs2 99 sa8 7 1 7 9 sb6 0 2 59 s c 3 3 33 9 sa7 20 bs1 1 0 0 s c 8 6 1 8 0 sa6 0 2 60 sb33 3 4 0 sc6 21 vdd 1 01 sb8 6 1 8 1 sc5 9 2 6 1 sa33 3 4 1 sb6 22 nc 1 0 2 sa8 6 1 8 2 sb5 9 2 62 s c 3 2 34 2 sa6 23 nc 1 0 3 s c 8 5 1 8 3 sa5 9 2 63 sb32 3 4 3 sc5 24 nc 1 0 4 sb8 5 1 8 4 sc5 8 2 6 4 sa32 3 4 4 sb5 25 vbr e f 1 0 5 sa8 5 1 8 5 sb5 8 2 65 s c 3 1 34 5 sa5 26 nc 1 0 6 s c 8 4 1 8 6 sa5 8 2 66 sb31 3 4 6 sc4 27 f b 1 0 7 sb8 4 1 8 7 sc5 7 2 6 7 sa31 3 4 7 sb4 28 vdd b 1 0 8 sa8 4 1 8 8 sb5 7 2 68 s c 3 0 34 8 sa4 29 gdr 1 09 sc83 18 9 sa5 7 2 69 sb30 3 4 9 sc3 30 vss 1 1 0 sb8 3 1 9 0 sc5 6 2 7 0 sa30 3 5 0 sb3 31 nc 1 1 1 sa8 3 1 9 1 sb5 6 2 71 s c 2 9 35 1 sa3 32 nc 1 1 2 s c 8 2 1 9 2 sa5 6 2 72 sb29 3 5 2 sc2 33 nc 1 1 3 sb8 2 1 9 3 sc5 5 2 7 3 sa29 3 5 3 sb2 34 nc 1 1 4 sa8 2 1 9 4 sb5 5 2 74 s c 2 8 35 4 sa2 35 com 6 3 1 15 sc81 19 5 sa5 5 2 75 sb28 3 5 5 sc1 36 co m 6 1 1 16 sb8 1 1 9 6 sc5 4 2 7 6 sa28 3 5 6 sb1 37 co m 5 9 1 17 sa8 1 1 9 7 sb5 4 2 77 s c 2 7 35 7 sa1 38 com 5 7 1 18 sc80 19 8 sa5 4 2 78 sb27 3 5 8 sc0 39 co m 5 5 1 19 sb8 0 1 9 9 sc5 3 2 7 9 sa27 3 5 9 sb0 40 co m 5 3 1 20 sa8 0 2 0 0 sb5 3 2 80 s c 2 6 36 0 sa0 41 com 51 1 21 sc79 20 1 sa5 3 2 81 sb26 36 1 nc 42 co m 4 9 1 22 sb7 9 2 0 2 sc5 2 2 8 2 sa26 3 6 2 n c 43 com 4 7 1 23 sa7 9 2 0 3 sb5 2 2 83 s c 2 5 36 3 n c 44 com 45 1 24 sc78 20 4 sa5 2 2 84 sb25 36 4 nc 45 co m 4 3 1 25 sb7 8 2 0 5 sc5 1 2 8 5 sa25 3 6 5 n c 46 com 4 1 1 26 sa7 8 2 0 6 sb5 1 2 86 s c 2 4 36 6 n c 47 com 3 9 1 27 sc77 20 7 sa5 1 2 87 sb24 3 6 7 com 0 48 co m 3 7 1 28 sb7 7 2 0 8 sc5 0 2 8 8 sa24 3 6 8 co m 2 49 com 3 5 1 29 sa7 7 2 0 9 sb5 0 2 89 s c 2 3 36 9 c om 4 50 com 3 3 1 30 sc76 21 0 sa5 0 2 90 sb23 3 7 0 com 6 51 co m 3 1 1 31 sb7 6 2 1 1 sc4 9 2 9 1 sa23 3 7 1 co m 8 52 com 2 9 1 32 sa7 6 2 1 2 sb4 9 2 92 s c 2 2 37 2 c om 1 0 53 com 2 7 1 33 sc75 21 3 sa4 9 2 93 sb22 3 7 3 com 1 2 54 co m 2 5 1 34 sb7 5 2 1 4 sc4 8 2 9 4 sa22 3 7 4 co m 1 4 55 com 2 3 1 35 sa7 5 2 1 5 sb4 8 2 95 s c 2 1 37 5 c om 1 6 56 com 2 1 1 36 sc74 21 6 sa4 8 2 96 sb21 3 7 6 com 1 8 57 co m 1 9 1 37 sb7 4 2 1 7 sc4 7 2 9 7 sa21 3 7 7 co m 2 0 58 com 1 7 1 38 sa7 4 2 1 8 sb4 7 2 98 s c 2 0 37 8 c om 2 2 59 com 1 5 1 39 sc73 21 9 sa4 7 2 99 sb20 3 7 9 com 2 4 60 co m 1 3 1 40 sb7 3 2 2 0 sc4 6 3 0 0 sa20 3 8 0 co m 2 6 61 com 1 1 1 41 sa7 3 2 2 1 sb4 6 3 01 s c 1 9 38 1 c om 2 8 62 co m 9 1 4 2 s c 7 2 2 2 2 sa4 6 3 02 sb19 3 8 2 co m 3 0 6 3 c om 7 14 3 s b 72 2 23 s c 45 30 3 s a 1 9 3 83 c om 32 6 4 c om 5 14 4 s a 72 2 24 s b 45 30 4 s c 18 3 84 c om 34 65 co m 3 1 4 5 s c 7 1 2 2 5 sa4 5 3 05 sb18 3 8 5 co m 3 6 6 6 c om 1 14 6 s b 71 2 26 s c 44 30 6 s a 1 8 3 86 c om 38 6 7 n c 14 7 s a 71 2 27 s b 44 30 7 s c 17 3 87 c om 40 68 nc 1 4 8 s c 7 0 2 2 8 sa4 4 3 08 sb17 3 8 8 co m 4 2 6 9 n c 14 9 s b 70 2 29 s c 43 30 9 s a 1 7 3 89 c om 44 7 0 n c 15 0 s a 70 2 30 s b 43 31 0 s c 16 3 90 c om 46 71 nc 1 5 1 s c 6 9 2 3 1 sa4 3 3 11 sb16 3 9 1 co m 4 8 7 2 n c 15 2 s b 69 2 32 s c 42 31 2 s a 1 6 3 92 c om 50 7 3 s c 95 15 3 s a 69 2 33 s b 42 31 3 s c 15 3 93 c om 52 74 sb95 1 54 sc 68 23 4 sa4 2 3 14 sb15 3 9 4 co m 5 4 75 sa95 1 55 sb6 8 2 3 5 sc4 1 3 1 5 sa15 3 9 5 co m 5 6 7 6 s c 94 15 6 s a 68 2 36 s b 41 31 6 s c 14 3 96 c om 58 77 sb94 1 57 sc 67 23 7 sa4 1 3 17 sb14 3 9 7 co m 6 0 78 sa94 1 58 sb6 7 2 3 8 sc4 0 3 1 8 sa14 3 9 8 co m 6 2 79 sc9 3 1 5 9 sa6 7 2 3 9 sb4 0 3 19 s c 1 3 39 9 n c 80 sb93 1 60 sc 66 24 0 sa4 0 3 20 sb13 4 0 0 n c
solom on s y s t e c h nov 2007 p 64/68 rev 1.2 SSD1331 14.4 SSD1331u3 r 1 cof package di mensions f i g u re 44 - ssd133 1u 3r1 o u tlin e d ra w in g s s d 1 3 3 1 u 3
SSD1331 rev 1.2 p 65/68 nov 2007 s o l o mo n s y st ec h
solom on s y s t e c h nov 2007 p 66/68 rev 1.2 SSD1331 14.5 SSD1331u3 r 1 cof package pi n assignment f i g u re 45 - ssd133 1u 3r1 p i n assig n men t d ra w in g
SSD1331 rev 1.2 p 67/68 nov 2007 s o l o mo n s y st ec h t a b l e 23 - ssd133 1u 3r1 p i n assig n m en t p i n no . p in na m e p i n n o. p i n n a m e p i n no. p i n na m e p i n no . p i n na m e p i n no. p i n na m e p i n no. p i n na m e 1 n c 8 1 s a 9 3 161 sb 66 2 4 1 s c39 3 21 s a 13 401 nc 2 v cc 82 sc92 162 sa 66 2 4 2 s b39 3 22 s c 12 3 v com h 83 s b 9 2 163 s c 65 2 4 3 s a39 3 23 s b 12 4 n c 8 4 s a 9 2 164 sb 65 2 4 4 s c38 3 24 s a 12 5 d 7 8 5 s c91 165 sa 65 2 4 5 s b38 3 25 s c 11 6 d 6 86 s b 9 1 166 s c 64 2 46 s a38 3 26 s b 11 7 d 5 8 7 s a 9 1 167 sb 64 2 4 7 s c37 3 27 s a 11 8 d 4 8 8 s c90 168 sa 64 2 4 8 s b37 3 28 s c 10 9 d 3 89 s b 9 0 169 s c 63 2 49 s a37 3 29 s b 10 10 d2 90 s a 9 0 170 sb 63 2 5 0 s c36 3 30 s a 10 11 d1 91 sc89 171 sa 63 2 5 1 s b36 3 31 sc9 12 d0 92 s b 8 9 172 s c 62 2 5 2 s a36 3 32 s b 9 13 e / rd# 93 s a 8 9 173 sb 62 2 5 3 s c35 3 33 s a 9 14 r/ w # 94 sc88 174 sa 62 2 5 4 s b35 3 34 sc8 15 d/c# 95 s b 8 8 175 s c 61 2 5 5 s a35 3 35 s b 8 16 res # 96 s a 8 8 176 sb 61 2 5 6 s c34 3 36 s a 8 17 cs # 97 s c87 177 sa 61 2 57 s b34 3 37 sc7 18 fr 98 s b 8 7 178 s c 60 2 58 s a34 3 38 s b 7 19 i r e f 99 s a 8 7 179 sb 60 2 5 9 s c33 3 39 s a 7 20 b s 2 1 0 0 sc86 180 sa 60 2 6 0 s b33 3 40 sc6 21 b s 1 10 1 s b 8 6 181 s c 59 2 61 s a33 3 41 s b 6 22 v ddi o 10 2 s a 8 6 182 sb 59 2 62 s c32 3 42 s a 6 23 v d d 1 0 3 sc85 183 sa 59 2 6 3 s b32 3 43 sc5 24 vci r 10 4 s b 8 5 184 s c 58 2 6 4 s a32 3 44 s b 5 25 v b re f 1 0 5 s a 8 5 185 sb 58 2 6 5 s c31 3 45 s a 5 26 nc 10 6 s c84 186 sa 58 2 6 6 s b31 3 46 sc4 27 f b 10 7 s b 8 4 187 s c 57 2 67 s a31 3 47 s b 4 28 vddb 10 8 s a 8 4 188 sb 57 2 6 8 s c30 3 48 s a 4 29 gdr 1 0 9 sc83 189 sa 57 2 6 9 s b30 3 49 sc3 30 vs s 1 1 0 s b 8 3 190 s c 56 2 7 0 s a30 3 50 s b 3 31 nc 11 1 s a 8 3 191 sb 56 2 7 1 s c29 3 51 s a 3 32 nc 11 2 s c82 192 sa 56 2 7 2 s b29 3 52 sc2 33 nc 11 3 s b 8 2 193 s c 55 2 7 3 s a29 3 53 s b 2 34 nc 11 4 s a 8 2 194 sb 55 2 7 4 s c28 3 54 s a 2 35 com 6 3 1 1 5 sc81 195 sa 55 2 7 5 s b28 3 55 sc1 36 com 61 11 6 s b 8 1 196 s c 54 2 76 s a28 3 56 s b 1 37 com 59 11 7 s a 8 1 197 sb 54 2 77 s c27 3 57 s a 1 38 com 5 7 1 1 8 sc80 198 sa 54 2 7 8 s b27 3 58 sc0 39 com 55 11 9 s b 8 0 199 s c 53 2 79 s a27 3 59 s b 0 40 com 53 12 0 s a 8 0 200 sb 53 2 80 s c26 3 60 s a 0 41 com 5 1 1 2 1 sc79 201 sa 53 2 8 1 s b26 3 61 nc 42 com 4 9 1 2 2 s b 7 9 202 s c 52 2 8 2 s a26 3 62 nc 43 com 4 7 1 2 3 s a 7 9 203 sb 52 2 8 3 s c25 3 63 nc 44 com 4 5 1 2 4 sc78 204 sa 52 2 8 4 s b25 3 64 nc 45 com 4 3 1 2 5 s b 7 8 205 s c 51 2 8 5 s a25 3 65 nc 46 com 4 1 1 2 6 s a 7 8 206 sb 51 2 8 6 s c24 3 66 nc 47 com 3 9 1 2 7 sc77 207 sa 51 2 8 7 s b24 3 67 com 0 48 com 3 7 1 2 8 s b 7 7 208 s c 50 2 8 8 s a24 3 68 com 2 49 com 3 5 1 2 9 s a 7 7 209 sb 50 2 8 9 s c23 3 69 com 4 50 com 3 3 1 3 0 sc76 210 sa 50 2 9 0 s b23 3 70 com 6 51 com 3 1 1 3 1 s b 7 6 211 s c 49 2 9 1 s a23 3 71 com 8 52 com 29 13 2 s a 7 6 212 sb 49 2 92 s c22 3 72 com 1 0 53 com 2 7 1 3 3 sc75 213 sa 49 2 9 3 s b22 3 73 com 1 2 54 com 25 13 4 s b 7 5 214 s c 48 2 94 s a22 3 74 com 1 4 55 com 23 13 5 s a 7 5 215 sb 48 2 95 s c21 3 75 com 1 6 56 com 2 1 1 3 6 sc74 216 sa 48 2 9 6 s b21 3 76 com 1 8 57 com 19 13 7 s b 7 4 217 s c 47 2 97 s a21 3 77 com 2 0 58 com 17 13 8 s a 7 4 218 sb 47 2 98 s c20 3 78 com 2 2 59 com 1 5 1 3 9 sc73 219 sa 47 2 9 9 s b20 3 79 com 2 4 60 com 13 14 0 s b 7 3 220 s c 46 3 00 s a20 3 80 com 2 6 61 com 11 14 1 s a 7 3 221 sb 46 3 01 s c19 3 81 com 2 8 62 com 9 14 2 s c72 222 sa 46 3 02 s b19 3 82 com 3 0 63 com 7 14 3 s b 7 2 223 s c 45 3 03 s a19 3 83 com 3 2 64 com 5 14 4 s a 7 2 224 sb 45 3 04 s c18 3 84 com 3 4 65 com 3 14 5 s c71 225 sa 45 3 05 s b18 3 85 com 3 6 66 com 1 14 6 s b 7 1 226 s c 44 3 06 s a18 3 86 com 3 8 67 nc 14 7 s a 7 1 227 sb 44 3 0 7 s c17 3 87 com 4 0 68 nc 14 8 s c70 228 sa 44 3 0 8 s b17 3 88 com 4 2 69 nc 14 9 s b 7 0 229 s c 43 3 0 9 s a17 3 89 com 4 4 70 nc 15 0 s a 7 0 230 sb 43 3 1 0 s c16 3 90 com 4 6 71 nc 15 1 s c69 231 sa 43 3 1 1 s b16 3 91 com 4 8 72 nc 15 2 s b 6 9 232 s c 42 3 1 2 s a16 3 92 com 5 0 73 s c 9 5 15 3 s a 6 9 233 sb 42 3 13 s c15 3 93 com 5 2 74 sb 95 15 4 s c68 234 sa 42 3 1 4 s b15 3 94 com 5 4 75 sa 95 15 5 s b 6 8 235 s c 41 3 15 s a15 3 95 com 5 6 76 s c 9 4 15 6 s a 6 8 236 sb 41 3 16 s c14 3 96 com 5 8 77 sb 94 15 7 s c67 237 sa 41 3 1 7 s b14 3 97 com 6 0 78 sa 94 15 8 s b 6 7 238 s c 40 3 18 s a14 3 98 com 6 2 79 s c 9 3 15 9 s a 6 7 239 sb 40 3 1 9 s c13 3 99 nc 80 sb 93 16 0 s c66 240 sa 40 3 2 0 s b13 4 00 nc
solom on s y s t e c h nov 2007 p 68/68 rev 1.2 SSD1331 solomon sy ste c h reserv es the ri ght to ma ke cha nge s w i thout fu rthe r noti c e to any pro ducts herein . s olo mon sy stech makes no w arr anty , repres e nt a t i on o r g uarant ee regardin g t he s uitabilit y o f i t s pro ducts f o r any p art i c ular pu rpose, n or d oes solomon s y s t ec h a s s u me any liab ility ari s ing out o f the appli c a t i on or use o f any product or cir c ui t, and s pecifi c ally disclaims any and al l liabili ty , incl uding w ithout li mi tatio n consequen tial o r inciden tal damage s. ?ty pical? par ameters can and do v ary in diff eren t appli c ation s . all o pera t in g parame t er s, i nclu ding ?ty pica l s ? must be v a lidated for each cu stomer app lica t ion by custome r?s te chni cal ex perts. solomon sy ste c h doe s not co n v e y any licen se under its pa tent righ ts n or the rights o f other s. solomon s y stech prod ucts ar e not de signe d, in tended, o r authori z e d for u s e a s compo nents in sy stems in tended for surgi c al implant in to the body , or o t her appl ications in tended to su ppor t or su stai n life, or fo r a n y oth e r appli c a t ion in which the failure o f the solom on sy ste c h produ ct could crea te a si tua t ion w here personal in j u ry or death may occu r. should buy er purchase or u s e solomon sy ste c h products for any su c h unin t end ed or unauthor ized appl ication , buy e r shall in demnify and hold s o lomon sy ste c h an d its offi ces, emplo y ees, subsid iarie s , affil iate s , an d di stri butor s h a rmless against all cl aims, costs, damage s, a nd ex pense s , and reasona ble attorn e y fees ari s ing ou t of, dir e ctly or i ndire ctly , a n y clai m of p ersonal inj ury or death a s socia t ed w ith su ch uni nten de d or un autho rize d use, ev en i f such cl aim alleg es that so lomon sy ste c h w as negli gent re gard in g the de sign or manufa c tur e o f the part all sol o mon sy stech products compl i ed w i th si x (6) hazard ous substances l i m i t ati on requi remen t per europ ean uni on (eu ) ?restri c ti on of h a zardous subst ance (ro h s) di recti v e (2002/95/ ec)? and c hi na standard ? ?????? (sj/t11364 -200 6)? w i th contr o l marki ng s y mbol . hazardo u s substances test report i s avai l abl e upon req ueste d. http://www.solo mon-systech.com

▲Up To Search▲

Price & Availability of SSD1331

	To Download SSD1331 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .